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PINS DESCRIPTI O N

PIN

ACTIVE

TYPE

DESCRIPTION

clk

-

input

Global system clock

rst

Low

input

Global system reset

prgdata[7:0]

-

input

Program memory bus input

datai[7:0]

-

input

Memory bus input

ufrdatai[7:0]

-

input

UFRs data bus input

ready

Low

input

Code and Data memory Ready

irq

*

input

Interrupt input

portai[7:0]

-

input

Port A input

portbi[7:0]

-

input

Port B input

portci[7:0]

-

input

Port C input

portdi[7:0]

-

input

Port D input

cap1,2

Low

input

Capture inputs

rxd

Low

input

SCI receiver data input

clkdocd

-

input

DoCD

docddatai

-

input

DoCD

prgaddr[15:0]

-

output

Program memory address bus

prgoe

-

output

Program memory output enable

datao[7:0]

-

output

Data memory & UFR bus output

addr[15:0]

-

output

Data memory address bus

ramwe

Low

output

Data memory write enable

ramoe

Low

output

Data memory output enable

ufraddr[5:0]

-

output

UFR’s address bus

ufrwe

Low

output

UFRs write enable

ufroe

Low

output

UFRs output enable

halt

High

output

Halt clock system (STOP inst.)

portao[7:0]

-

output

Port A output

portbo[7:0]

-

output

Port B output

portco[7:0]

-

output

Port C output

portdo[7:0]

-

output

Port D output

ddra[7:0]

-

output

Port A data direction control

ddrb[7:0]

-

output

Port B data direction control

ddrc[7:0]

-

output

Port C data direction control

ddrd[7:0]

-

output

Port D data direction control

cmp1,2

*

output

Compare outputs

txd

Low

output

SCI transmitter data output

docddatao

-

output

DoCD

docdclk

-

output

DoCD

prgwe

-

output

DoCD

* Kind of activity is configurable

SYMBOL

addr(15:0)

ramwe

ramoe

portao(7:0)

portdo(7:0)

portco(7:0)

portbo(7:0)

portai(7:0)

portbi(7:0)

portci(7:0)

portdi(7:0)

datai(7:0)

ufrdatai(7:0)

irq

cap1

cap2

clk

rst

rxd

datao(7:0)

txd

halt

ddra(7:0)

ddrd(7:0)

ddrc(7:0)

ddrb(7:0)

cmp1

cmp2

prgdata(7:0)

prgaddr(15:0)

prgoe

ready

ufraddr(5:0)

ufrwe

ufroe

clkdocd

docddatai

docddatao

docdclk

prgwe

DoCD

BLOCK DIAGRAM

Control Unit

- Performs the core synchroniza-

tion and data flow control. This module man-

ages execution of all instructions. The Control

Unit also manages execution of STOP instruc-

tion and wakes-up the processor from the

STOP mode.

Opcode Decoder

- Performs an instruction

opcode decoding and the control functions for

all other blocks.

ALU

- Arithmetic Logic Unit performs the

arithmetic and logic operations during execu-

tion of an instruction. It contains accumulator

(A), Condition Code Register (CCREG), Index

registers (X) and related logic like arithmetic

unit, logic unit and multiplier.