TMPR4951B datasheet(29/256 Pages) TOSHIBA

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Handling Precautions

3.3.3

Derating

The term “derating” refers to ensuring greater device reliability by setting operating ranges reduced from rated

values and taking into consideration factors such as current surges and noise.

While derating generally applies to electrical stresses such as voltage, current and power, and environmental

stresses such as ambient temperature and humidity, it differs from application to application. Refer to the

individual technical datasheets available for each product. Power devices in particular require heat sink

consideration as well since the level of derating greatly affects reliability.

For your reference, details are provided in the appendix. Be sure to read the appendix carefully.

3.3.4

Unused Pins

If unused pins are left open, some devices exhibit input instability, resulting in faulty operation such as a sudden

increase in current consumption. In addition, if unused output pins on a device are connected to the power

supply, GND or other output pin, the IC may malfunction or break down.

Since the treatment of unused input and output pins differs for each product and pin, please follow the directions

in the individual technical datasheets and databooks.

CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can readily

pick up noise and become unstable. In this case, if the input reaches an intermediate level, both the P-channel

and N-channel transistors will become conductive, allowing unnecessary power supply current to flow. It is

therefore necessary to ensure that the unused input gates of a device are connected to the power supply pin or

ground (GND) pin of the same device. For treatment of heat sink pins, refer to the individual technical

datasheets and databooks.

3.3.5

Latch-up

Semiconductor devices sometimes transition to an inherent condition referred to as “latch-up.” This condition

mainly occurs in CMOS devices. This happens when a parasitic PN-PN junction (thyristor structure) built in the

device itself is turned on, causing a large current to flow between the power supply voltage and GND,

eventually causing the device to break down.

Latch-up occurs when the voltage impressed on an input or output pin exceeds the rated value, causing a large

current to flow in the internal element, or when the voltage impressed on the power supply voltage pin exceeds

its rated value, forcing the internal element to breakdown. Once the element falls into the latch-up state, even

though the excess voltage may have been applied only for an instant, the large current continues to flow between

the power supply voltage and GND, potentially causing device explosion or combustion. To avoid this problem,

observe the following:

(1) Do not allow the voltage levels on the input and output pins to rise above the power supply voltage or

decrease below GND. Consider the timing during power supply activation as well.

(2) Do not allow any abnormal noises to be applied to the device.

(3) Set the electrical potential of unused input pins to the power supply voltage or GND.

(4) Do not create an output short.

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