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LPC2364 датащи(PDF) 12 Page - NXP Semiconductors |
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LPC2364 датащи(HTML) 12 Page - NXP Semiconductors |
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12 / 47 page ![]() LPC2364_66_68_2 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 — 1 October 2007 12 of 47 NXP Semiconductors LPC2364/66/68 Fast communication chip [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input, digital section of the pad is disabled. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [4] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [6] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis [7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis [8] Pad provides special analog functionality. [9] Pad provides special analog functionality. [10] Pad provides special analog functionality. [11] Pad provides special analog functionality. [12] Pad provides special analog functionality. [13] Pad provides special analog functionality. RTCK 100[1] I/O RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT 14[1] O RSTOUT — This is a 1.8 V pin. LOW on this pin indicates LPC2364/66/68 being in Reset state. RESET 17[7] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22[8] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23[8] O Output from the oscillator amplifier. RTCX1 16[8] I Input to the RTC oscillator circuit. RTCX2 18[8] O Output from the RTC oscillator circuit. VSS 15, 31, 41, 55, 72, 97, 83[9] I ground: 0 V reference. VSSA 11[10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, 71, 96[11] I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(DCDC)(3V3) 13, 42, 84[12] I 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the on-chip DC-to-DC converter only. VDDA 10[13] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. VREF 12[13] I ADC reference: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19[13] I RTC power supply: 3.3 V on this pin supplies the power to the RTC. Table 3. Pin description …continued Symbol Pin Type Description |
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