LPC2364 datasheet(17/47 Pages) NXP

17 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

17 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a speciﬁc hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If

requests from two channels become active at the same time the channel with the

highest priority is serviced ﬁrst.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

• One AHB bus master for transferring data. This interface transfers data when a DMA

request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efﬁciently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

• Internal four-word FIFO per channel.

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

LPC2364/66/68 use accelerated GPIO functions:

• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

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