LPC2131 datasheet(29/39 Pages) NXP

29 / 39 page

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

29 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

[4]

VDD supply voltages must be present.

[5]

3-state outputs go into 3-state mode when VDD is grounded.

[6]

Accounts for 100 mV voltage drop in all supply lines.

[7]

Only allowed for a short time period.

[8]

Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.

[9]

Applies to P1.16 to P1.25.

[10] On pin VBAT.

[11] Optimized for low battery consumption.

[12] The input threshold voltage of I2C-bus pins meets the I2C-bus speciﬁcation, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

[13] To VSS.

[1]

The ADC is monotonic, there are no missing codes.

[2]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.

[3]

The integral no-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 7.

[4]

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 7.

[5]

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 7.

[6]

The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated A/D and the ideal transfer curve. See Figure 7.

Table 7.

ADC static characteristics

VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C, unless otherwise speciﬁed; ADC frequency 4.5 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIA

analog input voltage

VDDA

Cia

analog input

capacitance

--1

differential linearity error

VSSA =0V, VDDA = 3.3 V

[1][2] --

±1

LSB

EL(adj)

integral non-linearity

VSSA =0V, VDDA = 3.3 V

[3] --

±2

LSB

offset error

VSSA =0V, VDDA = 3.3 V

[4] --

±3

LSB

gain error

VSSA =0V, VDDA = 3.3 V

[5] --

±0.5

absolute error

VSSA =0V, VDDA = 3.3 V

[6] --

±4

LSB

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