LPC2131 datasheet(18/39 Pages) NXP

18 / 39 page

LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

18 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

• Built-in baud rate generator.

• Standard modem interface signals included on UART1. (LPC2134/36/38 only)

• The LPC2131/32/34/36/38 transmission FIFO control enables implementation of

software (XON/XOFF) ﬂow control on both UARTs and hardware (CTS/RTS) ﬂow

control on the LPC2134/36/38 UART1 only.

6.10.2 UART features available in LPC213x/01 only

• Fractional baud rate generator enables standard baud rates such as 115200 to be

achieved with any crystal frequency above 2 MHz.

• Auto-bauding.

• Auto-CTS/RTS ﬂow-control fully implemented in hardware (LPC2134/36/38 only).

6.11 I2C-bus serial I/O controller

The LPC2131/32/34/36/38 each contain two I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

This I2C-bus implementation supports bit rates up to 400 kbit/s (Fast I2C).

6.11.1 Features

• Standard I2C compliant bus interface.

• Easy to conﬁgure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus may be used for test and diagnostic purposes.

6.12 SPI serial I/O controller

The LPC2131/32/34/36/38 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to be able to handle multiple masters and slaves connected to a given

bus. Only a single master and a single slave can communicate on the interface during a

given data transfer. During a data transfer the master always sends a byte of data to the

slave, and the slave always sends a byte of data to the master.

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