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SCI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

8-19

and the external clock is used if the SCI is the slave device, as noted above. The clock is gated

and limited to a maximum frequency equal to one eighth of the DSP core operating frequency

(that is, 12.5 MHz for a DSP core frequency of 100 MHz).

For asynchronous operation, the SCI can use the internal and external clocks in any combination

as the source clocks for the TX clock and RX clock. If an external clock is used for the SCLK

input, it must be sixteen times the desired bit rate (designated as the 16

× clock), as indicated in

Figure 8-6. When the internal clock is used to supply a clock to an external device, the clock can

use the actual bit rate (designated as the 1

× clock) or the 16 × clock rate, as determined by the

COD bit. The output clock is continuous.

When SCKP is cleared, the transmitted data on the TXD signal changes on the negative edge of

the serial clock and is stable on the positive edge. When SCKP is set, the data changes on the

positive edge and is stable on the negative edge. The received data on the RXD signal is sampled

on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the serial clock.

8.6.4 SCI Data Registers

The SCI data registers are divided into two groups: receive and transmit, as shown in Figure 8-7.

There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive

Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX

or STXA) and a parallel-to-serial Transmit Shift Register.

Figure 8-6. 16 x Serial Clock

RX, TX Data

(SSFTD = 0)

Idle Line

Start

Select 8-or 9-bit Words

x1 Clock

x16 Clock

(SCKP = 0)

234567

Stop

Start

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