DSP56303 datasheet(145/292 Pages) FREESCALE

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ESSI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

7-13

This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals and

Registers, on page 7-33 covers ESSI GPIO.

7.5.1 ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct

the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word

length, and number of words per frame for serial data.

Figure 7-2. ESSI Control Register A(CRA)

SSC1

WL2

WL1

WL0

ALC

DC4

DC3

DC2

DC1

DC0

7654

3210

PSR

PM7

PM6

PM5

PM4

PM3

PM2

PM1

PM0

—Reserved bit; read as 0; write to 0 for future compatibility.

(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)

Table 7-3. ESSI Control Register A (CRA) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

Reserved. Write to 0 for future compatibility.

SSC1

Select SC1

Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is

configured in Synchronous mode (the CRB synchronous/asynchronous bit

(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then

the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1

signal is configured as output (SCD1 = 1). This configuration enables an

external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is

configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled

(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is

configured as output (SCD1 = 1).

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