DSP56303 datasheet(140/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

7-8

Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI)

exception occurs regardless of the transmit mask register setting. The transmit last slot

interrupt can signal that the transmit mask slot register can be reset, the DMA channels

can be reconfigured, and data memory pointers can be reassigned. Using the Transmit Last

Slot interrupt guarantees that the previous frame is serviced with the previous frame

settings and the new frame is serviced with the new frame settings without

synchronization problems.

Note:

The maximum transmit last slot interrupt service time should not exceed

N – 1 ESSI bits service time (where N is the number of bits in a slot).

ESSI transmit data:

Occurs when the transmit interrupt is enabled, at least one of the enabled transmit data

registers is empty, and no transmitter error conditions exist. Write to all the enabled TX

registers or to the TSR to clear this interrupt. This error-free interrupt uses a fast interrupt

service routine for minimum overhead (if no more than two transmitters are used).

To configure an ESSI exception, perform the following steps:

Configure the interrupt service routine (ISR):

Load vector base address register

VBA (b23:8)

Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,

I_VEC must be defined for the assembler before the interrupt equate file is

included.

Load the exception vector table entry: two-word fast interrupt, or jump/branch to

subroutine (long interrupt).

p:I_SI0TD

Configure interrupt trigger; preload transmit data

Enable and prioritize overall peripheral interrupt functionality.

IPRP (S0L1:0)

Write data to all enabled transmit registers.

TX00

Enable a peripheral interrupt-generating function.CRB (TE0)

Enable a specific peripheral interrupt.

CRB0 (TIE)

Enable peripheral and associated signals.

PCRC (PC[5–0])

Unmask interrupts at the global level.

SR (I1–0)

The example material to the right of the steps shows register settings for configuring an

ESSI0 transmit interrupt using transmitter 0. The order of the steps is optional except

that the interrupt trigger configuration must not be completed until the ISR

configuration is complete. Since step 2c may cause an immediate transmit without

generating an interrupt, perform the transmit data preload in step 2b before step 2c to

ensure that valid data is sent in the first transmission.

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