DSP56303 datasheet(115/292 Pages) FREESCALE

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DSP Core Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

6-15

6.6.4 Host Data Register (HDR)

The HDR register holds the data value of the corresponding bits of the HI08 signals configured as

GPIO signals. The functionality of Dxx depends on the corresponding HDDR bit (that is,

DRxx).The host processor can not access the Host Data Register (HDR)

6.6.5 Host Base Address Register (HBAR)

In multiplexed bus modes, HBAR selects the base address where the host-side registers are

mapped into the host bus address space. The address from the host bus is compared with the base

address as programmed in the Base Address Register. An internal chip select is generated if a

match is found. Figure 6-11 shows how the chip-select logic uses HBAR.

D15

D14

D13

D12

D11

D10

Figure 6-9. Host Data Register (HDR) (X:$FFFFC8)

Table 6-10. HDR and HDDR Functionality

HDDR

HDR

DRxx

Dxx

GPIO Signal1

Non-GPIO Signal1

Read-only bit—The value read is the binary value of

the signal. The corresponding signal is configured as

an input.

Read-only bit—Does not contain significant data.

Read/write bit— The value written is the value read.

The corresponding signal is configured as an output

and is driven with the data written to Dxx.

Read/write bit— The value written is the value read.

1. Defined by the selected configuration.

9876

54321

BA10

BA9

BA8

BA7

BA6

BA5

BA4

BA3

—Reserved bit, read as 0, write to 0 for future compatibility.

Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)

Table 6-11. Host Base Address Register (HBAR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

15–8

Reserved. Write to 0 for future compatibility.

7–0

BA[10–3]

$80

Base Address

Reflect the base address where the host-side registers are mapped into

the bus address space.

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