DSP56303 datasheet(247/292 Pages) FREESCALE

247 / 292 page

Internal I/O Memory Map

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

B-3

DMA

$FFF4

$FFFFF4

DMA Status Register (DSTR)

$FFF3

$FFFFF3

DMA Offset Register 0 (DOR0)

$FFF2

$FFFFF2

DMA Offset Register 1 (DOR1)

$FFF1

$FFFFF1

DMA Offset Register 2 (DOR2)

$FFF0

$FFFFF0

DMA Offset Register 3 (DOR3)

DMA0

$FFEF

$FFFFEF

DMA Source Address Register (DSR0)

$FFEE

$FFFFEE

DMA Destination Address Register (DDR0)

$FFED

$FFFFED

DMA Counter (DCO0)

$FFEC

$FFFFEC

DMA Control Register (DCR0)

DMA1

$FFEB

$FFFFEB

DMA Source Address Register (DSR1)

$FFEA

$FFFFEA

DMA Destination Address Register (DDR1)

$FFE9

$FFFFE9

DMA Counter (DCO1)

$FFE8

$FFFFE8

DMA Control Register (DCR1)

DMA2

$FFE7

$FFFFE7

DMA Source Address Register (DSR2)

$FFE6

$FFFFE6

DMA Destination Address Register (DDR2)

$FFE5

$FFFFE5

DMA Counter (DCO2)

$FFE4

$FFFFE4

DMA Control Register (DCR2)

DMA3

$FFE3

$FFFFE3

DMA Source Address Register (DSR3)

$FFE2

$FFFFE2

DMA Destination Address Register (DDR3)

$FFE1

$FFFFE1

DMA Counter (DCO3)

$FFE0

$FFFFE0

DMA Control Register (DCR3)

DMA4

$FFDF

$FFFFDF

DMA Source Address Register (DSR4)

$FFDE

$FFFFDE

DMA Destination Address Register (DDR4)

$FFDD

$FFFFDD

DMA Counter (DCO4)

$FFDC

$FFFFDC

DMA Control Register (DCR4)

DMA5

$FFDB

$FFFFDB

DMA Source Address Register (DSR5)

$FFDA

$FFFFDA

DMA Destination Address Register (DDR5)

$FFD9

$FFFFD9

DMA Counter (DCO5)

$FFD8

$FFFFD8

DMA Control Register (DCR5)

Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)

Peripheral

16-Bit Address

24-Bit Address

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