DSP56303 datasheet(216/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

9-24

Freescale Semiconductor

Triple Timer Module

9.4.4 Timer Control/Status Register (TCSR)

The TCSR is a read/write register controlling the timer and reflecting its status.

TCF

TOF

PCE

DIR

TRM

INV

TC3

TC2

TC1

TC0

TCIE

TOIE

Reserved. Read as 0. Write to 0 for future compatibility

Figure 9-23. Timer Control/Status Register (TCSR)

Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

23–22

Reserved. Write to zero for future compatibility.

TCF

Timer Compare Flag

Indicate that the event count is complete. In timer, PWM, and watchdog

modes, the TCF bit is set after (M – N + 1) events are counted. (M is the

value in the compare register and N is the TLR value.) In measurement

modes, the TCF bit is set when the measurement completes. Writing a one to

the TCF bit clears it. A zero written to the TCF bit has no effect. The bit is also

cleared when the timer compare interrupt is serviced. The TCF bit is cleared

by a hardware RESET signal, a software RESET instruction, the STOP

instruction, or by clearing the TCSR[TE] bit to disable the timer.

Note:

The TOF and TCF bits are cleared by a 1 written to the specific bit.

To ensure that only the target bit is cleared, do not use the BSET

command. The proper way to clear these bits is to write 1, using a

MOVEP instruction, to the flag to be cleared and 0 to the other flag.

TOF

Timer Overflow Flag

Indicates that a counter overflow has occurred. This bit is cleared by writing a

one to the TOF bit. Writing a zero to TOF has no effect. The bit is also cleared

when the timer overflow interrupt is serviced. The TOF bit is cleared by a

hardware RESET signal, a software RESET instruction, the STOP

instruction, or by clearing the TCSR[TE] bit to disable the timer

19–16

Reserved. Write to zero for future compatibility.

PCE

Prescaler Clock Enable

Selects the prescaler clock as the timer source clock. When PCE is cleared,

the timer uses either an internal (CLK/2) signal or an external (TIO) signal as

its source clock. When PCE is set, the prescaler output is the timer source

clock for the counter, regardless of the timer operating mode. To ensure

proper operation, the PCE bit is changed only when the timer is disabled. The

PS[1–0] bits of the TPLR determine which source clock is used for the

prescaler. A timer can be clocked by a prescaler clock that is derived from the

TIO of another timer.

Reserved. Write to zero for future compatibility.

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