SC312XDP512F0MPVR datasheet(154/1350 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

154

Freescale Semiconductor

In either level or edge triggered modes, the ﬁrst conversion begins when the trigger is received. In both

cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger

circuitry.

After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be

triggered externally.

If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion

sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger remains asserted

in level mode while a sequence is completing, another sequence will be triggered immediately.

4.4.2.2

General-Purpose Digital Input Port Operation

The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are

multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external

input data that can be accessed through the digital port registers (PORTAD0 & PORTAD1) (input-only).

The analog/digital multiplex operation is performed in the input pads. The input pad is always connected

to the analog inputs of the ATD10B16C. The input pad signal is buffered to the digital port registers. This

buffer can be turned on or off with the ATDDIEN0 & ATDDIEN1 register. This is important so that the

buffer does not draw excess current when analog potentials are presented at its input.

4.4.3

Operation in Low Power Modes

The ATD10B16C can be conﬁgured for lower MCU power consumption in three different ways:

•

Stop Mode

Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due

to the recovery time the result of this conversion should be ignored.

Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power

standby mode. This halts any conversion sequence in progress. During recovery from stop mode,

there must be a minimum delay for the stop recovery time tSR before initiating a new ATD

conversion sequence.

•

Wait Mode

Wait Mode with AWAI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D

conversion, but due to the recovery time the result of this conversion should be ignored.

Entering wait mode, the ATD conversion either continues or halts for low power depending on the

logical value of the AWAIT bit.

•

Freeze Mode

Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D

conversion in progress.

In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0

bits. This is useful for debugging and emulation.

NOTE

The reset value for the ADPU bit is zero. Therefore, when this module is

reset, it is reset into the power down state.

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