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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 151 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 151 Page - Freescale Semiconductor, Inc |
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151 / 1350 page  Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 151 4.3.2.16 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 4.3.2.16.1 Left Justified Result Data 76543210 R (10-BIT) R (8-BIT) BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 W Reset 00000000 = Unimplemented or Reserved Figure 4-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH) 76543210 R (10-BIT) R (8-BIT) BIT 1 u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 00000000 = Unimplemented or Reserved u = Unaffected Figure 4-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL) |
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