SC312XDP512F0MPVR datasheet(90/1350 Pages) FREESCALE

90 / 1350 page

Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

2.3.2.7

CRG PLL Control Register (PLLCTL)

This register controls the PLL functionality.

Read: Anytime

Write: Refer to each bit for individual write conditions

76543210

CME

PLLON

AUTO

ACQ

FSTWKP

PRE

PCE

SCME

Reset

11110001

Figure 2-10. CRG PLL Control Register (PLLCTL)

Table 2-5. PLLCTL Field Descriptions

Field

Description

CME

Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.

0 Clock monitor is disabled.

1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self clock

mode.

Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality, this could cause

unpredictable operation of the MCU!

Note: In stop mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss

of external clock will not be detected. Also after wake-up from stop mode (PSTP = 0) with fast wake-up

enabled (FSTWKP = 1) the clock monitor is disabled independently of the CME bit setting and any loss of

external clock will not be detected.

PLLON

Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self clock mode, the PLL is turned on, but the

PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.

0 PLL is turned off.

1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.

AUTO

Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low

bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime

except when PLLWAI = 1, because PLLWAI sets the AUTO bit to 1.

0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.

1 Automatic mode control is enabled and ACQ bit has no effect.

ACQ

Acquisition Bit

Write anytime. If AUTO=1 this bit has no effect.

0 Low bandwidth ﬁlter is selected.

1 High bandwidth ﬁlter is selected.

FSTWKP

Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If

self-clock mode is disabled (SCME = 0) this bit has no effect.

0 Fast wake-up from full stop mode is disabled.

1 Fast wake-up from full stop mode is enabled.

When waking up from full stop mode the system will immediately resume operation i self-clock mode (see

Section 2.4.1.4, “Clock Quality Checker”). The SCMIF ﬂag will not be set. The system will remain in self-clock

mode with oscillator and clock monitor disabled until FSTWKP bit is cleared. The clearing of FSTWKP will

start the oscillator, the clock monitor and the clock quality check. If the clock quality check is successful, the

CRG will switch all system clocks to OSCCLK. The SCMIF ﬂag will be set. See application examples in

Figure 2-23 and Figure 2-24.

SC312XDP512F0MPVR датащи(PDF) 90 Page - Freescale Semiconductor, Inc

SC312XDP512F0MPVR датащи(HTML) 90 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL