SC312XDP512F0MPVR datasheet(136/1350 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

136

Freescale Semiconductor

FIFO

Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the

result registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result

If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion

sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning

conversion sequence, the result register counter will wrap around when it reaches the end of the result register

ﬁle. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register

ﬁle, the current conversion result will be placed.

Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the

conversion counter even if FIFO=1. So the ﬁrst result of a new conversion sequence, started by writing to

ATDCTL5, will always be place in the ﬁrst result register (ATDDDR0). Intended usage of FIFO mode is

continuos conversion (SCAN=1) or triggered conversion (ETRIG=1).

Finally, which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear

mode may or may not be useful in a particular application to track valid data.

0 Conversion results are placed in the corresponding result register up to the selected sequence length.

1 Conversion results are placed in consecutive result registers (wrap around at end).

1:0

FRZ[1:0]

Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the

ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond

to a breakpoint as shown in Table 4-10. Leakage onto the storage node and comparator reference capacitors

may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze

period.

Table 4-9. Conversion Sequence Length Coding

S8C

S4C

S2C

S1C

Number of Conversions

per Sequence

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Table 4-8. ATDCTL3 Field Descriptions (continued)

Field

Description

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