SC312XDP512F0MPVR datasheet(133/1350 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

133

Read: Anytime

Write: Anytime

76543210

ADPU

AFFC

AWAI

ETRIGLE

ETRIGP

ETRIGE

ASCIE

ASCIF

Reset

00000000

= Unimplemented or Reserved

Figure 4-5. ATD Control Register 2 (ATDCTL2)

Table 4-6. ATDCTL2 Field Descriptions

Field

Description

ADPU

ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power

consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time

period after ADPU bit is enabled.

0 Power down ATD

1 Normal ATD functionality

AFFC

ATD Fast Flag Clear All

0 ATD ﬂag clearing operates normally (read the status register ATDSTAT1 before reading the result register

to clear the associate CCF ﬂag).

1 Changes all ATD conversion complete ﬂags to a fast clear sequence. Any access to a result register will

cause the associate CCF ﬂag to clear automatically.

AWAI

ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the

ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down,

the ATD requires a recovery time period after exit from Wait mode.

0 ATD continues to run in Wait mode

1 Halt conversion and power down ATD during Wait mode

After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of

this conversion should be ignored.

ETRIGLE

External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See

Table 4-7 for details.

ETRIGP

External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 4-7 for

details.

ETRIGE

External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of

the ETRIG[3:0] inputs as described in Table 4-5. If external trigger source is one of the AD channels, the digital

input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with

external events.

0 Disable external trigger

1 Enable external trigger

ASCIE

ATD Sequence Complete Interrupt Enable

0 ATD Sequence Complete interrupt requests are disabled.

1 ATD Interrupt will be requested whenever ASCIF = 1 is set.

ASCIF

ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF ﬂag equals the SCF ﬂag (see

Section 4.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.

0 No ATD interrupt occurred

1 ATD sequence complete interrupt pending

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