SC312XDP512F0MPVR datasheet(104/1350 Pages) FREESCALE

104 / 1350 page

Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.17

104

Freescale Semiconductor

2.4.2.2

Self Clock Mode

The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due

to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO

running at minimum operating frequency; this mode of operation is called self clock mode. This requires

CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self clock mode, the

PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically

select OSCCLK to be the system clock and return to normal mode. Section 2.4.1.4, “Clock Quality

Checker” for more information on entering and leaving self clock mode.

NOTE

In order to detect a potential clock loss the CME bit should be always

enabled (CME = 1)!

If CME bit is disabled and the MCU is conﬁgured to run on PLL clock

(PLLCLK), a loss of external clock (OSCCLK) will not be detected and will

cause the system clock to drift towards the VCO’s minimum frequency

fSCM. As soon as the external clock is available again the system clock

ramps up to its PLL target frequency. If the MCU is running on external

clock any loss of clock will cause the system to go static.

2.4.3

Low Power Options

This section summarizes the low power options available in the CRG.

2.4.3.1

Run Mode

The RTI can be stopped by setting the associated rate select bits to 0.

The COP can be stopped by setting the associated rate select bits to 0.

2.4.3.2

Wait Mode

The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of

the individual bits in the CLKSEL register. All individual wait mode conﬁguration bits can be superposed.

This provides enhanced granularity in reducing the level of power consumption during wait mode.

Table 2-11 lists the individual conﬁguration bits and the parts of the MCU that are affected in wait mode

After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG

then checks whether the PLLWAI bit is asserted (Figure 2-21). Depending on the conﬁguration, the CRG

switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the PLL. As

soon as all clocks are switched off wait mode is active.

Table 2-11. MCU Conﬁguration During Wait Mode

PLLWAI

RTIWAI

COPWAI

PLL

Stopped

—

RTI

—

Stopped

—

COP

—

Stopped

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