SC312XDP512F0MPVR datasheet(103/1350 Pages) FREESCALE

103 / 1350 page

Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

103

NOTE

Remember that in parallel to additional actions caused by self clock mode

or clock monitor reset1 handling the clock quality checker continues to

check the OSCCLK signal.

The clock quality checker enables the PLL and the voltage regulator

(VREG) anytime a clock check has to be performed. An ongoing clock

quality check could also cause a running PLL (fSCM) and an active VREG

during pseudo stop mode or wait mode.

2.4.1.5

Computer Operating Properly Watchdog (COP)

The COP (free running watchdog timer) enables the user to check that a program is running and

sequencing properly. When the COP is being used, software is responsible for keeping the COP from

timing out. If the COP times out it is an indication that the software is no longer being executed in the

intended sequence; thus a system reset is initiated (see Section 2.4.1.5, “Computer Operating Properly

Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register

allow selection of seven COP time-out periods.

When COP is enabled, the program must write 0x_55 and 0x_AA (in this order) to the ARMCOP register

during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program

fails to do this and the COP times out, the part will reset. Also, if any value other than 0x_55 or 0x_AA is

written, the part is immediately reset.

Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to

the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.

A premature write will immediately reset the part.

If PCE bit is set, the COP will continue to run in pseudo stop mode.

2.4.1.6

Real Time Interrupt (RTI)

The RTI can be used to generate a hardware interrupt at a ﬁxed periodic rate. If enabled (by setting

RTIE = 1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated

OSCCLK. At the end of the RTI time-out period the RTIF ﬂag is set to 1 and a new RTI time-out period

starts immediately.

A write to the RTICTL register restarts the RTI time-out period.

If the PRE bit is set, the RTI will continue to run in pseudo stop mode.

2.4.2

Operating Modes

2.4.2.1

Normal Mode

The CRG block behaves as described within this speciﬁcation in all normal modes.

1. A Clock Monitor Reset will always set the SCME bit to logical 1.

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