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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 327 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 327 Page - Freescale Semiconductor, Inc |
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327 / 1350 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 327 7.3.2.11 Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. 76543210 R TOI 000 TCRE PR2 PR1 PR0 W Reset 00000000 = Unimplemented or Reserved Figure 7-16. Timer System Control Register 2 (TSCR2) Table 7-14. TSCR2 Field Descriptions Field Description 7 TOI Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled. 1 Hardware interrupt requested when TOF flag set. 3 TCRE Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output compare. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset disabled and counter free runs. 1 Counter reset by a successful output compare on channel 7. Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000. 2:0 PR[2:0] Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. See Table 7-15. Table 7-15. Prescaler Selection PR2 PR1 PR0 Prescale Factor 00 0 1 00 1 2 01 0 4 01 1 8 10 0 16 10 1 32 11 0 64 1 1 1 128 |
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