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SC312XDP512F0MPVR датащи(PDF) 324 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 324 Page - Freescale Semiconductor, Inc |
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324 / 1350 page ![]() Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.17 324 Freescale Semiconductor 7.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Read or write: Anytime All bits reset to zero. NOTE To enable output action by OMx and OLx bits on timer port, the corresponding bit in OC7M should be cleared. 76543210 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W Reset 00000000 Figure 7-11. Timer Control Register 1 (TCTL1) 76543210 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W Reset 00000000 Figure 7-12. Timer Control Register 2 (TCTL2) Table 7-9. TCTL1/TCTL2 Field Descriptions Field Description OM[7:0] 7, 5, 3, 1 OMx — Output Mode OLx — Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx. See Table 7-10. OL[7:0] 6, 4, 2, 0 Table 7-10. Compare Result Output Action OMx OLx Action 0 0 Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one |
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