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CD4049B датащи(PDF) 3 Page - Silicon Supplies

номер детали CD4049B
подробное описание детали  CMOS High Voltage Logic
PDF  5 Pages
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производитель  SS [Silicon Supplies]
домашняя страница  https://siliconsupplies.com/
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CD4049B датащи(HTML) 3 Page - Silicon Supplies

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CMOS High Voltage Logic – CD4049B
Rev 1.0
21/11/17
PARAMETER
SYMBOL
MIN
MAX
UNITS
Supply Voltage
VDD
3.0
18
V
DC Input Voltage
4
VIN
0
VDD
V
Operating Temperature Range
TJ
-55
+125
°C
Recommended Operating Conditions3 (Voltages referenced to V
SS)
Absolute Maximum Ratings1
PARAMETER
SYMBOL
VALUE
UNIT
DC Supply Voltage (Referenced to VSS)
VDD
-0.5 to +20
V
DC Input Voltage
2 (Referenced to V
SS)
VIN
VDD to +18
V
DC Output Voltage (Referenced to VSS)
VOUT
-0.5 to VDD +0.5
V
Storage Temperature Range
TSTG
-65 to 150
°C
Input Current (per Pad)
IIN, IOUT
±10
mA
Power Dissipation in Still Air
2
PD
750
mW
DC Electrical Characteristics (Voltages referenced to V
SS)
LIMITS
PARAMETER
SYMBOL
VDD
CONDITIONS
25°C
85°C
FULL RANGE
5
UNITS
5V
VOUT = 0.5V
4
4
4
10V
VOUT = 1.0V
8
8
8
Minimum High-Level
Input Voltage
VIH
15V
VOUT = 1.5V
12.5
12.5
12.5
V
5V
VOUT = VDD -0.5V
1
1
1
10V
VOUT = VDD -1.0V
2
2
2
Maximum Low-Level
Input Voltage
VIL
15V
VOUT = VDD -1.5V
2.5
2.5
2.5
V
5V
4.95
4.95
4.95
10V
9.95
9.95
9.95
Minimum High-Level
Output Voltage
VOH
15V
VIN = VSS
14.95
14.95
14.95
V
5V
0.05
0.05
0.05
10V
0.05
0.05
0.05
Maximum Low-Level
Output Voltage
VOL
15V
VIN = VDD
0.05
0.05
0.05
V
Maximum Input
Leakage Current
IIN
18V
VIN = VDD or VSS
±0.1
±.0.1
±1.0
µA
5V
1
1
30
10V
2
2
60
15V
4
4
120
Maximum Quiescent
Supply Leakage
Current
IDD
20V
VIN = VDD or VSS
IOUT = 0µA
20
20
600
µA
3.  This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pad
only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high−impedance circuit. For
proper operation, the ranges VSS ≤ VIN ≤ 18 V and VSS ≤ VOUT ≤ VDD are recommended. Unused inputs must always be tied to an appropriate logic
voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 4. VIN ≤ VDD is not recommended. High-to-Low level conversion only.
1.  Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may
reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.



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