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CMOS High Voltage Logic – CD4049B

Rev 1.0

21/11/17

6. Not production tested in die form, characterized by chip design and tested in package.

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

5

UNITS

4.5V

VIN = VDD or VSS

VOL = 0.4V

3.3

2.6

1.8

5V

VIN = VDD or VSS

VOL = 0.4V

4

3.2

2.4

10V

VIN = VDD or VSS

VOL = 0.5V

10

8

5.6

Minimum Output

Low (Sink) Current

IOL

15V

VIN = VDD or VSS

VOL = 1.5V

26

24

18

mA

5V

VIN = VDD or VSS

VOH = 2.5V

-2.6

-2.1

-1.55

5V

VIN = VDD or VSS

VOH = 4.6V

-0.81

-0.65

-0.48

10V

VIN = VDD or VSS

VOH = 9.5V

-2.0

-1.65

-1.18

Minimum Output

High (Source)

Current

IOH

15V

VIN = VDD or VSS

VOH = 13.5V

-5.2

-4.3

-3.1

mA

 

DC Electrical Characteristics Continued (Voltages referenced to V

SS)

AC Electrical Characteristics6

LIMITS

PARAMETER

SYMBOL

VIN

VDD

CONDITIONS

25°C

85°C

FULL RANGE

5

UNITS

5V

5V

120

120

240

10V

10V

65

65

130

10V

5V

90

90

180

15V

15V

50

50

100

Maximum

Propagation

Delay, Input A to

Output Y

(Figure 1)

tPLH

15V

5V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

90

90

180

ns

5V

5V

65

65

130

10V

10V

40

40

80

10V

5V

30

30

60

15V

15V

30

30

60

Maximum

Propagation

Delay, Input A to

Output Y

(Figure 1)

tPHL

15V

5V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

20

20

40

ns

5V

5V

160

160

320

10V

10V

80

80

160

Output

Transition Time,

Any Output

(Figure 1)

tTLH

15V

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

60

60

120

ns

5. -55˚C ≤ TJ ≤ +125˚C