CMOS High Voltage Logic – CD4013B

 

Dual D-Type Flip-Flop Logic IC with Set and Reset in bare die form

Rev 1.0

21/11/17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1400 x 1500

55 x 59

µm

mils

Minimum Bond Pad Size

100 x 100

3.94 x 3.94

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

High Input Voltage up to 20V

Symmetrical Output Characteristics

Max input current 1µA at 18V over full Military

Temperature Range

Set-Reset Capability & Static Flip-Flop Operation  

Drives x2 Low–power TTL or x1 LSTTL Load

Direct drop-in replacement for obsolete

components in long term programs.

Features:

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

Description

The CD4013B is fabricated using a 3µm 15CMOS

process and consists of two identical, independent

data type flip-flops. Each flip-flop has separate data,

set, reset, clock inputs and Q,Q outputs. The device

can be used in Shift Register applications and also

Counter or Toggle applications by connecting Q output

to the data input. The logic level present at the “D”

input is transferred to the Q output during the positive-

going transition of the clock pulse. Setting or resetting

is clock independent and accomplished by a high level

on the respective Set or Reset line.

Ordering Information

Die Dimensions in µm (mils)

1400 (55)

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (100 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

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