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AC Electrical Characteristics5

5 Not production tested in die form, characterized by chip design and tested in package.

.

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

3.5

3.5

3

10V

8

8

6

Maximum Clock

Frequency

fmax

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

12

12

10

MHz

5V

300

300

450

10V

130

130

200

Propagation Delay,

Clock to Q or Q

(Figure 1)

tPLH, tPHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

90

90

150

ns

5V

300

300

450

10V

130

130

200

Propagation Delay,

Set to Q or Reset to

Q (Figure 2)

tPLH

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

90

90

150

ns

5V

400

400

600

10V

170

170

250

Propagation Delay,

Set to Q or Reset to

Q (Figure 2)

tPHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

120

120

150

ns

5V

200

200

250

10V

100

100

150

Output Transition

Time, Any Output

(Figure 1)

tTLH, tTHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

80

80

100

ns

Input Capacitance

CIN

-

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

7.5

7.5

7.5

pF

CMOS High Voltage Logic – CD4013B

Rev 1.0

21/11/17

Timing Requirements5

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

140

140

200

10V

60

60

80

Minimum Pulse

Width, Clock

(Figure 1)

tw

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

40

40

50

ns

5V

180

180

250

10V

80

80

120

Minimum Pulse

Width, Set or Reset

(Figure 2)

tw

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

50

50

80

ns

5V

40

40

40

10V

20

20

20

Minimum Setup

Time, Data to Clock

tsu

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

15

15

15

ns

5V

5

5

8

10V

5

5

5

Minimum Hold Time,

Clock to Data

th

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

5

5

5

ns

5V

500

500

500

10V

30

30

30

Maximum Input Rise

or Fall Time, Clock

(Figure 1)

tr, tf

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

6

6

6

ns