King Billion Electronics Co., Ltd

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HF88M02

January 16, 2004

Page 7 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

DIR00

RS = 100 & OEn = '0'

RS = 101 & OEn = '0'

RS = 111 & OEn = '0'

RS = 110 & OEn = '0'

P00

D0

P10

1

0

QD

QD

P00

DIR00

1

0

Q

D

DIR10

Q

P10

D

There are seven internal registers used to provide the functionality of Data file as well as Expansion I/O

capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except AC2. AC2

~ AC0 are write-only and constitute the complete 19-bit Address Counter used as pointer to the data.

While the P0, P1, DIR0 and DIR1 can be read as well as written. Their initial values are as indicated in

the following table. When RS2 = ‘0’, the RS1 ~ RS0 are ignored, the Address Counter can be loaded or

contents of Data File can be read. This is to reduce the required pin needed for external MCU to

interface with the Device and also simplify the procedure for loading the address counter.

The P0, P1, DIR0, and DIR1 are used for expansion I/O registers. The P0 and P1 are output registers of

Expansion I/O and DIR0 and DIR1 are the Direction Registers that determine the I/O mode of P0 and P1.

Each pin can be configured as output or input mode individually by setting or resetting the corresponding

pin of the DIR registers. Initially, both P0 and P1 are default to input mode at ‘Hi’ state.

The accesses to the internal registers will be inhibited when CEn is ‘1’. However, the status of internal

registers, such as expansion I/O ports, will not be affected. For example, if a certain pin is in output

mode and driving ‘Hi’, it will not change when CEn pin goes to ‘1’ state. Therefore, the users are

advised to take care of the power down condition of I/O ports when entering sleep mode to prevent

unnecessary power drain.

Type

Description

Initial Value

R

Read data by Indirect access

0xx

AC2

W

Address latch 2 for A17 ~ A16

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