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HF88M02

January 16, 2004

Page 4 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

4 Pin Description

HF88M02-PLCC32

11

2

9

8

7

6

5

29

28

24

27

23

25

13

21

22

12

26

P01

P02

P03

P04

P05

P06

P07

P16

P15

OE

P10

P12

P13

D0

D7

CE

P00

P11

Symbol

Pin No. I/O

Description

VDD

32

P Positive power supply input pin.

VSS

16

P Gound pin.

CEn

22

I

The CEn (Chip Enable) input is the device selection and power control for

internal Mask ROM array. Whenever CEn goes high, the internal Mask

ROM will enter standby (power saving) mode and accesses to internal

registers are inhibited. Otherwise, it is in active mode and the contents of

the ROM and registers can be accessed. Please note that only accesses to

the internal registers are inhibited, but the status of I/O registers are not

affected by the CEn pin and will remain unchanged. CEn is also useful to

uniquely select a certain device for applications where multiple-chip array is

required.

WEn

1

I

WEn controls writing to internal registers such as the Output Port Registers,

Direction Registers, Address Counter and Data on D7 ~ D0 are latched on

the rising edge of the WE pulse. The WEn (Write Enable) input is internally

pulled-up to VDD to prevent pin floating. So this pin should stay at ‘1’

state when inactive to prevent unintended current consumption.

OEn

24

I

OEn (Output Enable) is the output control which gates ROM array data,

expansion I/O ports, Direction Registers to the data I/O pins D7 ~ D0. The

internal Address Counter will automatically increment by one with each

rising edge of OEn pin in Sequentially Read mode.

RS2~RS0

I

Register Select pins RS2 ~ RS0 for accessing ROM data, Address Counter,

as well as expansion I/O ports. The RS2 (Register Select) input is internally

pulled-down to Ground. So this pin should stay at ‘0’ state when inactive to

prevent unintended current drain.

P17 ~ P10

I/O Bi-directional I/O port P1.

P07 ~ P00

I/O Bi-directional I/O port P0.