RT9232BGS datasheet(10/14 Pages) RICHTEK

10 / 14 page

RT9232B

DS9232B-03

March 2007

www.richtek.com

Application Information

The RT9232B is a single-phase synchronous buck PWM

DC-DC controller designed to drive two N-MOSFETs. It

provides a highly accurate, programmable output voltage

precisely regulated to low voltage requirement with an

internal 0.8V

±1% reference.

Initialization

The RT9232B automatically initiates its softstart cycle

only after VCC and VIN power and chip enabling signals

are ready. There is no special power-on sequence should

be took care especially while implement the chip in. The

internal Power-On Reset (POR) logic continually monitors

the voltage level of input power and enabling pin; in which

the IC supply power is monitored via VCC pin and input

power VIN is via OCSET pin. An internal current source

with driving capability of 200uA causes a fixed voltage

drop across the resistor connecting VIN to OCSET pin.

The RT9232B internal logic will deem the input voltage

ready once the voltage of OCSET pin is high than 1.5V.

The preferred VIN ready level could be set by selecting an

appropriate resistor ROCSET as :

Once all voltages of VCC, OCSET, and EN pins ramp

higher than the internal specific thresholds. The internal

POR logic will initialize the softstart operation then.

Moreover, the POR inhibits driver operation while pulling

the EN pin low. Transitioning EN pin high after input supply

voltages ready to initialize soft-start operation.

Soft-Start

The behavior of RT9232B Soft-Start can be simply

described as shown in Figure.1 below; and the Soft-Start

can be sliced to several time-frames with specific operation

respectively.

T0~T1

The RT9232B initiates the softstart cycle as shown in

Figure 1 when POR function is OK. An internal 10uA current

source charges an external capacitor on SS pin (Css) to

5V. The softstart function produces an SSE signal that is

equal to SS

−0.8V. Error Amplifier (EA) and PWM

comparator are triple-input devices. The non-inverting input

whichever is smaller dominates the behavior of the devices.

During T0~T1, since SS is smaller than the sawtooth valley,

the PWM comparator outputs low no matter what the

COMP voltage is.

T1~T2

SSE ramps up and dominates the behavior of EA during

T1~T2. EA regulates COMP appropriately so that FB

ramps up along the SSE curve. The output voltage ramps

up accordingly. Thus upper MOSFET turns on at a limited

duty and output current overshoot can be reduced.

It is noted that lower MOSFET keeps off before the upper

MOSFET starts switching. This method provides smooth

start up when there is residual voltage on output capacitors.

The output voltage delay time and ramp up time are

calculated as Equation (1) and (2) respectively.

(2)

(1)

COMP

PWM

SSE

0.8V

Figure 1. Timing diagram of softstart

−

200

1.5V

IN_READY

SENSE

(s)

0.8V

−

(s)

0.8V

−

SSE

0.8V

COMP

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