RT9232GS datasheet(12/14 Pages) RICHTEK

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RT9232

DS9232-06 March 2007

www.richtek.com

Feedback Loop Design Procedure

Use these guidelines for locating the poles and zeros of

the compensation network:

1. Pick Gain (R2/R1) for desired 0dB crossing frequency

(FC).

2. Place 1ST zero FZ1 below modulator double pole FLC

(~75% FLC).

3. Place 2ND zero FZ2 at modulator double pole FLC.

4. Place 1ST pole FZ1 at the ESR zero FZ_ESR

5. Place 2ND pole FZ2 at half the switching frequency.

6. Check gain against error amplifier open-loop gain.

7. Pick RFB for desired output voltage.

8. Estimate phase margin and repeat if necessary.

Layout Consideration

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to the converter

instability. First, place the PWM power stage components.

Mount all the power components and connections in the

top layer with wide copper areas. The MOSFETs of Buck,

inductor, and output capacitor should be as close to each

other as possible. This can reduce the radiation of EMI

due to the high frequency current loop. If the output

capacitors are placed in parallel to reduce the ESR of

capacitor, equal sharing ripple current should be

considered. Place the input capacitor directly to the drain

Figure 5

FZ1

(12)

(13)

R3)

(R1

FZ2

(14)

FP1

(15)

FP2

OSC

ΔV

OSC

Driver

REF

PWM

Comparator

E/A

REF

OUT

COMP

ESR

PHASE

OUT

Figure 4

The compensation network consists of the error amplifier

EA and the impedance networks ZIN and ZFB. The goal of

the compensation network is to provide a closed loop

transfer function with the highest DC gain, the highest

0dB crossing frequency (FC) and adequate phase margin.

Typically, FC in range 1/5~1/10 of switching frequency is

adequate. The higher FC is, the faster dynamic response

is. A phase margin in the range of 45

°C~ 60°C is desirable.

The equations below relate the compensation network’s

poles, zeros and gain to the components (R1, R2, R3,

C1, C2, and C3) in Figure 4.

100

10K

100K

10M

-60

-40

-20

100

Modulator

Gain

ESR

Closed Loop Gain

Compensation

Gain

Open Loop Error

AMP Gain

20LOG

(VIN/ΔVOSC)

20LOG

(R1/R2)

Z1 FZ2

Frequency (Hz)

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