MP86905

– INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS

MP86905 Rev. 1.1

www.MonolithicPower.com

12

8/31/2020

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PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation. For best results, refer to Figure 3 and

follow the guidelines below.

1. Place the input MLCC capacitors as close

to VIN and PGND as possible.

2. Place the major MLCC capacitors on the

same layer as the MP86905.

3. Place

as

many

VIN and

PGND

vias

underneath the package as possible.

4. Place the vias between the VIN or PGND

long pads.

5. Place a VIN copper plane on the second

inner layer to form the PCB stack as VIN on

top, GND on the second layer, and VIN on

the

third

layer

to

reduce

parasitic

impedance from the input MLCC cap to the

MP86905.

6. Ensure that the copper plane on the inner

layer

at

least

covers

the

VIN

vias

underneath the package and input MLCC

capacitors.

7. Place more PGND vias close to the PGND

pin/pad

to

minimize

both

parasitic

resistance/impedance

and

thermal

resistance.

8. Place a BST

capacitor and

a VDRV

capacitor as close to the MP86905 pins as

possible. VDRV and BST capacitors size

0402 are recommended.

9. Use a trace width 20 mils or higher to route

the path.

10. Avoid the via for the BST driving path. It is

recommended to use a bootstrap capacitor

0.1µF to 1µF in a size 0402 package.

11. Place the VDD decoupling capacitor (size

0402) close to the device.

12. Connect AGND and PGND at the point of

the VDD capacitor's ground connection.

13. Keep the CS signal trace away from high

current paths like SW and PWM.

Figure 3: Example of PCB Layout (Placement & Top Layer PCB)

Input Capacitor: 1206 package (top side) and 0805 package (bottom side)

Inductor: 10x8 package

VDD/BST/VDRV capacitor: 0402 package

Via size: 20/10 mils

INDUCTOR

PGND

SW

20.6 mm

8mm

PWM

BST

VIN

SW

SW

VIN

PGND

16

17

3

4

13

14

15

22

23

20

21

18

1

19

2

12

11

6

5

8

7

10

9

RVDD

CVDD

CVDRV

CIN

VIN

CIN