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GL800HT25 датащи(PDF) 14 Page - GENESYS LOGIC

номер детали GL800HT25
подробное описание детали  USB 2.0 UTMI Compliant Transceiver IP Core
PDF  20 Pages
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производитель  GENESYS [GENESYS LOGIC]
домашняя страница  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL800HT25 датащи(HTML) 14 Page - GENESYS LOGIC

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GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
©2000-2003 Genesys Logic Inc.—All rights reserved.
Page 14
data for next transfer on the Data bus. If TXVLD is asserted and
TXRDY is negated, the SIE must hold the previously asserted data
on the Data bus. From the time TXVLD is negated, TXRDY is a
don’t care for the SIE.
D0~D15
27~30,
33~40,
43~46
B
Data bus 0~15
DVDD0
31
P
Positive digital supply (3.3V)
DVDD1
41
P
Positive digital supply
UMC 0.35um sample : 3.3V
TSMC 0.25um sample : 2.5V
DGND0~1
32,42
P
Digital ground (0V)
LINEST1
47
O
LINEST0
48
O
Line State. These signals reflect the current state of the single
ended receivers. They are combinatorial until a “usable” CLK30 is
available then they are synchronized to CLK30. They directly
reflect the current state of the DP (LineState[0]) and DM
(LineState[1]) signals:
DM DP Description
0
1
0: SE0
0
1
1: ‘J’ State
1
0
2: ‘K’ State
1
1
3: SE1
Notation:
Type
O
Output
I
Input
B
Bi-directional
B/I
Bi-directional, default input
B/O
Bi-directional, default output
P
Power / Ground
A
Analog
SO
Automatic output low when suspend
pu
Internal pull up
pd
Internal pull down
odpu
Open drain with internal pull up



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