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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F272 датащи(PDF) 174 Page - STMicroelectronics |
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ST10F272 датащи(HTML) 174 Page - STMicroelectronics |
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174 / 179 page  Electrical characteristics ST10F272 174/179 Figure 61. SSC master timing 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 24.8.20.2 Slave mode VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF 1st out bit Last out bit 2nd out bit 1) 2) 2nd In bit 1st in bit Last in bit SCLK MTSR MRST t308 t307 t308 t307 t305 t305 t300 t301 t302 t304 t303 t306 t305 Table 82. SSC slave mode timings Symbol Parameter Max. Baudrate 6.6 MBd (1)) @FCPU = 40MHz (<SSCBR> = 0002h) Variable Baudrate (<SSCBR> = 0001h - FFFFh) Unit min. max. min. max. t310 SR SSC clock cycle time(2) 150 150 8TCL 262144 TCL ns t311 SR SSC clock high time 63 – t310 / 2 – 12 – ns t312 SR SSC clock low time 63 – t310 / 2 – 12 – ns t313 SR SSC clock rise time – 10 – 10 ns t314 SR SSC clock fall time – 10 – 10 ns t315 CC Write data valid after shift edge – 55 – 2TCL + 30 ns t316 CC Write data hold after shift edge 0 – 0 – ns t317p SR Read data setup time before latch edge, phase error detection on (SSCPEN = 1) 62 – 4TCL + 12 – ns t318p SR Read data hold time after latch edge, phase error detection on (SSCPEN = 1) 87 – 6TCL + 12 – ns |
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