PI7C8152AMA datasheet(21/90 Pages) PERICOM

21 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 21 of 90

October 16, 2003 – Revision 1.11

3.6.2

MEMORY WRITE AND INVALIDATE

Posted write forwarding is used for Memory Write and Invalidate transactions.

The PI7C8152x disconnects Memory Write and Invalidate commands at aligned cache line

boundaries. The cache line size value in the cache line size register gives the number of

DWORD in a cache line.

If the value in the cache line size register does meet the memory write and invalidate

conditions, the PI7C8152x returns a target disconnect to the initiator on a cache line

boundary.

3.6.3

DELAYED WRITE TRANSACTIONS

Delayed write forwarding is used for I/O write transactions and Type 1 configuration write

transactions.

A delayed write transaction guarantees that the actual target response is returned back to

the initiator without holding the initiating bus in wait states. A delayed write transaction is

limited to a single DWORD data transfer.

When a write transaction is first detected on the initiator bus, and PI7C8152x forwards it as

a delayed transaction, PI7C8152x claims the access by asserting DEVSEL_L and returns a

target retry to the initiator. During the address phase, PI7C8152x samples the bus

command, address, and address parity one cycle later. After IRDY_L is asserted,

PI7C8152x also samples the first data DWORD, byte enable bits, and data parity. This

information is placed into the delayed transaction queue. The transaction is queued only if

no other existing delayed transactions have the same address and command, and if the

delayed transaction queue is not full. When the delayed write transaction moves to the head

of the delayed transaction queue and all ordering constraints with posted data are satisfied.

The PI7C8152x initiates the transaction on the target bus. PI7C8152x transfers the write

data to the target. If PI7C8152x receives a target retry in response to the write transaction

on the target bus, it continues to repeat the write transaction until the data transfer is

completed, or until an error condition is encountered.

If PI7C8152x is unable to deliver write data after 224 (default) or 232 (maximum) attempts,

PI7C8152x will report a system error. PI7C8152x also asserts P_SERR_L if the primary

SERR_L enable bit is set in the command register. See Section 6.4 for information on the

assertion of P_SERR_L. When the initiator repeats the same write transaction (same

command, address, byte enable bits, and data), and the completed delayed transaction is at

the head of the queue, the PI7C8152x claims the access by asserting DEVSEL_L and

returns TRDY_L to the initiator, to indicate that the write data was transferred. If the

initiator requests multiple DWORD, PI7C8152x also asserts STOP_L in conjunction with

TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid

byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH),

the corresponding byte of write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the

target, PI7C8152x returns a target retry to the initiator. PI7C8152x continues to return a

target retry to the initiator until write data is delivered to the target, or until an error

condition is encountered. When the write transaction is repeated, PI7C8152x does not

make a new entry into the delayed transaction queue. Section 3.9.3.1 provides detailed

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