PI7C8152AMA datasheet(85/90 Pages) PERICOM

85 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 85 of 90

October 16, 2003 – Revision 1.11

Bit

Function

Type

Description

PME_L Enable

R/O

Read as 0 as PI7C8152x does not support the PME_L pin.

12:9

Data Select

R/O

Read as 0 as the data register is not implemented.

14:13

Data Scale

R/O

Read as 0 as the data register is not implemented.

PME status

R/O

Read as 0 as the PME_L pin is not implemented.

12.1.42

PPB SUPPORT EXTENSIONS REGISER – OFFSET E0h

Bit

Function

Type

Description

21:16

Reserved

Reset to 0

B2_B3 Support

B2_B3 Support for D3HOT

When BPCCE is HIGH, this bit is read as ‘1’ to indicate that the

secondary clock outputs will be stopped and driven LOW when the

bridge is in D3HOT. This bit is not defined if BPCCE is read as ‘0’.

Bus Power /

Clock Control

Enable

Bus Power / Clock Control Enable

When BPCCE is pulled HIGH, this bit is read as ‘1’ to indicate that

the bus power/clock control is enabled. When the BPCCE is tied

LOW, this bit is read as ‘0’ to indicate that the bus power/clock is

disabled (secondary clocks are not disabled when this device is

placed in D3HOT).

BRIDGE BEHAVIOR

A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number

of possibilities. Those possibilities are summarized in the table below:

13.1

BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES

Initiator

Target

Response

Master on Primary

Target on Primary

PI7C8152x does not respond. It detects

this situation by decoding the address as

well as monitoring the P_DEVSEL_L for

other fast devices on the Primary Port.

Master on Primary

Target on Secondary

PI7C8152x asserts P_DEVSEL_L,

terminates the cycle normally if it is able

to be posted, otherwise return with a retry.

It then passes the cycle to the secondary

port. When the cycle is complete on the

target port, it will wait for the initiator to

repeat the same cycle and end with normal

termination.

Master on Primary

Target not on Primary nor

Secondary Port

PI7C8152x does not respond and the

cycle will terminate as master abort.

Master on Secondary

Target on the same

Secondary Port

PI7C8152x does not respond.

Master on Secondary

Target on Primary

PI7C8152x asserts S_DEVSEL_L,

terminates the cycle normally if it is able

to be posted, otherwise returns with a

retry. It then passes the cycle to the

primary port. When cycle is complete on

the target port, it will wait for the initiator

to repeat the same cycle and end with

normal termination.

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