12

© 2007 Semtech Corp.

www.semtech.com

SC192

PRELIMINARY

POWER MANAGEMENT

IN

OUT

OUT

IN

OUT

RMS

V

I

V

-

V

V

I

•

•

=

The worst case RMS ripple current occurs at a duty cycle

of 0.5 and its value at that point is

2

.

Ceramic capacitors are recommended for input capaci-

tors because of their low ESR and high ripple current

capabilities. In addition, it is advised that the input ca-

pacitor be placed as close to the input pin of the IC as

possible.

Layout Considerations

PCB layout is of utmost importance because the switch-

ing frequency is 750kHz with peak currents over 1A. A

careful layout will avoid potential stability and EMI prob-

lems. Traces should be as wide and as short as possible.

Keep the input capacitor as close to the package as pos-

sible. This will help minimize large loop areas. Keep the

power ground and analog ground separated and tie the

two together at one common point. Notice the top cop-

per Gerber plot (see Page 8), pin 3 and pin 10 are tied

together under the package. Be aware of the high cur-

rent paths and avoid tying signal grounds to the high power

grounds where the signal paths might experience large

fluctuations in voltages as high currents pass though

copper traces.

Applications Information Cont.

Efficiency at Vin = 3.6V

80

85

90

95

100

1

10305070

90

200 400 600

Load Curre nt (mA)

Vo = 2.5V

Vo = 1.8V

Line Regulation At Iout = 300mA

0.00

0.02

0.04

0.06

0.08

0.10

2.7

3.0

3.3

3.6

3.9

4.2

4.5

4.8

Input Voltage (Volts)

Vo = 1.8V

Load Regulation at Vin = 3.6V

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

1

20

40

60

80

100

200

300

400

500

600

Ouput Current (mA)

Vo = 1.8V

Vo = 2.5V

Efficiency at Vin = 5V

60

65

70

75

80

85

90

95

100

1

10

30

50

70

90

200

400

600

Load Current (mA)

Vo = 3.3V