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SC192

PRELIMINARY

POWER MANAGEMENT

Description

Description

The SC192 step-down, pulse-width-modulated (PWM),

DC-DC converter has an adjustable output range from

0.75V to the input voltage. The device has an internal

synchronous rectifier and does not require a schottky

diode on the LX pin.

At moderate to heavy loads, the converter operates in

the PWM mode with a fixed frequency of 750kHz. At light

loads the converter enters the power save mode by

modulating the frequency, pulse-frequency-modulation

(PFM) which achieves high efficiency under light load

conditions.

Normal Mode

This is a standard fixed frequency current mode topol-

ogy. The current feedback is through the PMOS current

path and is amplified and summed with the internal slope

compensation network and DC offset. The voltage feed-

back loop is through the resistor divider attached to the

ADJ pin. The transconductance error amplifier output is

the compensation (COMP) pin with the usual external

compensation network attached. The PWM COMP pin

closes the loop by comparing the summed current feed-

back and the COMP signal to determine the length of the

ON time. The period is set by the on-board oscillator or

external clock attached to the SYNC pin.

Power Save Mode

If SYNC/PWM is DC low, power save mode is used at

light loads to improve efficiency. When the output cur-

rent reaches a low enough level, the part goes into a

voltage hysteresis mode of operation. The current level

for this is set to be the current reversal protection on

the NMOS device. The output voltage is then allowed to

decay to a lower threshold with the part in a reduced

quiescent current (PSAVE) state. After this lower thresh-

old is reached the part is reawoken to normal operation,

but with a current offset on the COMP pin to drive the

output voltage regulation point to be above an upper

threshold point. However the offset is removed once the

upper threshold is reached. If the load current is now

sufficiently large the part will return to normal regulation,

if not another PSAVE cycle will start.

Frequency Foldback

When the ADJ pin is low the output switching frequency

is folded back in several discrete steps to protect against

a short to GND on the output and improve inrush cur-

rent control during start-up.

Forced PWM

If SYNC/PWM is DC high, the forced PWM mode is en-

abled. This ensures that the switching frequency of the

converter is maintained over the full range of output

loads. This means that the current reversal threshold of

the NMOS is changed to a negative value and the 100%

duty cycle and power save modes are also disabled.

100% Duty-Cycle Operation

Normally the control loop constrains the duty cycle of

the converter with minimum on and off times, but if the

output voltage droops to the lower power-save thresh-

old and the ON time is not terminated by the PWM com-

parator or PMOS current limit, then the next PMOS on

time is allowed to extend until either the PWM compara-

tor or PMOS current limit trips. This is then followed by a

minimum off time. This maximum on time/minimum off

time is allowed to continue until the upper power-save

threshold is reached. This allows the part to go into a

dropout mode of operation if the input supply collapses

down to the output voltage. If this happens, the output

voltage is equal to the input voltage minus the voltage

drop across the P-channel MOSFET.

Soft Start

The soft start mode is enabled after every shutdown cycle

to limit inrush current from the battery. In conjunction

with the frequency foldback this controls the maximum

current during start-up. The PMOS current limit is stepped

from 25%, to 50%, to 75%, and then 100% by an inter-

nal 2ms timer. As soon as the part reaches regulation,

soft start mode is disabled.