SC905AEVB datasheet(11/23 Pages) SEMTECH

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POWER MANAGEMENT

SC905A

means that these LDOs are on when there is a ‘1’ in their

respective bit locations (register 6, bit 3 for VTCXO, register

2, bit 6 for VMOT), or if their external enable pins are pulled

HIGH. To turn these LDOs off the I2C on/off control bit

must be ‘0’ and the external enable must be pulled LOW.

The state of EN_TCXO and EN_MOT can be established by

reading bits 0 and 2, respectively, in the Status Register.

VCSEL & VPSEL Pin

The VCSEL & VPSEL pins set the default voltage of CORE

and PAD LDOs respectively. When the VCSEL pin is set to

VIN the default voltage for the CORE LDO is 1.80V. When

this pin is set to GND the default voltage for the CORE LDO

is 1.35V. Likewise, when the VPSEL pin is set to VIN the

default voltage for the PAD LDO is 3.00V. When this pin is

set to GND, the default voltage for the PAD LDO is 2.20V.

In both cases the VCSEL and VPSEL pins must be tied to

GND or VIN prior to the device being powered on. This

voltage cannot change on the ﬂy by switching the pin

voltage between VIN or GND once the device is on. The

voltage can be changed from its default state after start-up

by writing to the appropriate voltage code register.

Active Shutdown

The shutdown control bits determine how the on-chip

active shutdown switches behave. Register 7 is the

active shutdown control register and is used to control the

shutdown behavior. Each LDO has a speciﬁc shutdown

bit assigned to it. When the active shutdown bit is enabled

(set to 1), the output capacitance on the LDO output is

discharged by an on-chip FET when the LDO is disabled.

When the active shutdown bit is disabled (set to 0), the

output capacitance on the LDO output is discharged by

the load. The default state for each LDO active shutdown

bit is on.

Default Status Bit

In many multi-threaded environments it is necessary to

maintain synchronization between the host micro-controller

and the target IC. The SC905A has a default status bit

(DSB) that will facilitate this task. The DSB can be useful

in keeping the MSM and the SC905A synchronized.

However, this is only useful if the MSM is powered by an

external switching regulator such as Semtech’s SC190A

switching regulator.

The DSB is bit 7 of register 0, and shares this register space

with the PAD voltage control bits. The DSB is only set to 1

during power-up to indicate that the part is set to the default

state. Moreover, the DSB cannot be written to a 1 through

the I2C interface the way the other bits in this register can;

it can only be cleared to 0 through the I2C interface. This

feature prevents a software race condition by always writing

to register 0 with bit 7 high when changing the PAD control

voltage. To clear the bit simply write a 0 to bit 7.

Applying the DSB

Upon power-up, the SC905A LDOs and internal registers are

set to their default state. The DSB is set to a 1 to indicate

that the SC905A is in its default state. Upon reading this

defaulted state condition, the MSM knows to perform

whatever synchronization is needed to set the SC905A

into a known user state. This user state is entered by a

two-stage process.

1) The MSM writes a 0 to the DSB indicating its desire to

modify the state of the SC905A. It then writes all of the

correct register information to the SC905A to set it to the

user state.

2) The MSM reads back all of the information to verify the

data. Then it reads back the DSB again to ensure it is

still set to 0. This veriﬁes that no reset took place during

the time that the multiple writes and read veriﬁcations

happened. If the DSB has been reset to 1, this process

needs to be repeated since the chip was reset sometime

during the initialization. Once the MSM and the SC905A

are synchronized, the DSB can be read back as a status

check periodically, as needed. If it is ever set back to the

default state, a new synchronization process is required.

This handshake-style protocol makes sure that the MSM

and SC905A are always synchronized.

LDO Power-On Sequence

When the SC905A ﬁrst turns on, the four LDOs that default

on are sequenced in the following fashion: 1) CORE, 2) PAD,

3) ANA, 4) TCXO. During the power-on sequence, there is

a 200μs delay between CORE and PAD to allow the output

of CORE to reach 1.2V before PAD is turned on, a delay of

100μs between PAD and ANA turning on, and a delay of

100μs between ANA and TCXO turning on. This process

eliminates large voltage spikes across the battery supply

during power-up. (For further information on LDO power

on sequencing, refer to the Timing Diagram on page 19.)

Applications Information (Cont.)

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