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POWER MANAGEMENT

SC900A

Applications Information (Cont.)

Layout Considerations

Layout is straightforward if you use the Gerber files on

page 21 as a reference. Notice that the input voltage feed

to the SC900A is on the bottom of the board and vias con-

nect this voltage track to the top of the board and then

to the SC900A itself. The input bypass can be one 4.7μF

capacitor, two 3.3μF capacitors, three 2.2μF capacitors or

five 1μF capacitors. The determining factor is how much

copper is available on the input voltage feed track and

how much room is available. If the input voltage track is

very thin, then use five 1μF capacitors placed very close

to the input pins of the SC900A. If the input track is fairly

thick, then you can use a single 4.7μF capacitor at the be-

ginning of the voltage feed track since a wider track has

less inductance per inch. The SC900AEVB has five 1μF

capacitors, but these can be replaced with one 4.7μF in

place of C1 and opens in place of C9, C14, C15, and C16

(see page 20 for details).

Register

Name

Register

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LDO A

LDO B

LDO C

LDO D

LDO E

LDO Reset

Control

On/Off Control

Register

0x00

0x01

0x02

0x03

0x04

0x05

0x06

XX

XX

X

LDOPGD Pin

Reset Polarity Bit

ARST Pin

Reset Polarity Bit

LDOPGD Monitor Logic Bits

LDOPGD Delay Bits

LDO (A) Reset Delay Bits

ON/OFF Control

LDO E

ON/OFF Control

LDO D

ON/OFF Control

LDO C

ON/OFF Control

LDO B

ON/OFF Control

LDO A

Active

Shutdown

1 = ON

0 = OFF

Output Voltage Codes

Table A for LDOs A & B

Table B for LDOs C, D & E

10

1

1

1

1

00

00

ON

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

LDO Reset Control Logic Table (Defaults are in Bold)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Result

Result

Result

Result

Result

LDOPGD Pin Polarity

ARST Pin Polarity

LDOPGD Monitor Logic

LDOPGD Delay

ARST Delay

1

0

1

0

1

0

00

0

00

0

0

00

0

0

1

11

1

11

1

1

11

1

High: Power Fail

Low: Power Good

High: Power Good

Low: Power Fail

High: Power Good

Low: Reset

High: Reset

Low: Power Good

LDOs

A, C, D & E

Good

LDO E Good

LDO C Good

LDO D Good

150ms

100ms

50ms

0ms

150ms

50ms

100ms

0ms

LDO Reset Control Logic Table (Defaults are in Bold)

Note:

Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST.

R/W

00

0

1

0

0

A0

X

DEVICE TYPE IDENTIFIER

DEVICE ADDRESS

SC900A Slave Address