SC900AEVB datasheet(10/23 Pages) SEMTECH

10 / 23 page

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POWER MANAGEMENT

SC900A

Applications Information

General Description

Each of the ﬁve low-dropout linear regulators (LDOs) can

be independently enabled or disabled and their output

voltages can each be set by an independent DAC. These

controls can be accessed through the I2C serial port.

There are ﬁve 8-bit volatile registers in the SC900A; one

for each LDO (registers A,B,C,D,E). In addition there is

one common reset and power good control register and

one on/off control register. The active shutdown circuitry

can be accessed through each LDO register (refer to the

section “Active Shutdown” on page 11 for more informa-

tion).

At power-up, the register contents are reset to their de-

fault values and the ARST for LDO A has a default start-up

delay of 100ms. At any time the part can be put into it’s

lowest power state (shutdown) by pulling the EN pin low.

Whenever the EN pin is forced low, the previous settings

are lost and the part requires reprogramming to return

to the desired state. When EN is pulled high, the device

starts up in the default state. A detailed description of the

protocol used to load the registers with data is described

in the section entitled “Using the I2C Interface” on page

14.

VIN and Enable Pin

The V

IN supply must be ≥ 2.7V before the EN pin can be

asserted. This means that the EN pin should not be tied

to V

IN so that it does not reach a logic high level before the

input supply reaches 2.7V.

LDOA (Core Supply)

LDOA is intended to be used as the core supply. It has an

output current capability of 200mA and a dedicated reset

signal ARST. INA is the dedicated input supply for this

regulator.

LDOB (Digital I/O Supply)

INB supplies power for the internal I2C interface and other

digital I/O functions, while LDOB supplies power for ARST

and LDOPGD output ports (see Block Diagram). There-

fore it is imperative that LDOB be operational to make use

of ARST and LDOPGD. If LDOB is turned off by the on/off

control register, these output ports will not function.

LDO RESET Control Register: ARST Pin

There are two functions that can be programmed, deﬁn-

ing the ARST pin action:

• Set the polarity of the reset signal

• Set the reset clear delay time in milliseconds

As soon as the LDOA output voltage falls below its pro-

grammed value, the ARST pin is asserted. The polarity of

the ARST pin can be set to active high or active low during

a reset condition, by bit 6 of the LDO Reset Control Reg-

ister. Once the error condition is resolved (output rises

to the programmed value), a delay is initiated before the

ARST pin is cleared. The delay is programmable by bits

0-1 of the LDO Reset Control Register. The Default delay

time is 100ms, and the delay can be programmed for 0,

50, 100, or 150ms.

LDOPGD Pin

There are three functions that can be programmed to

deﬁne the LDOPGD pin action:

• Set which LDOs are to be monitored for power good

• Set the polarity of the power good signal

• Set the power good delay time in milliseconds

Bits 4 and 5 of the LDO Reset Control Register select

which LDO or LDOs are monitored. LDO C, D and E can

be monitored independently or LDOs A, C, D, and E can

be monitored collectively. The polarity of the LDOPGD pin

can be set to active high or active low by bit 7 of the LDO

Reset Control Register. As soon as any of the selected LDO

output voltages which are monitored falls within spec, the

LDO power good (LDOPGD) pin is asserted. Once the LDO

output power is stable (output rises to the programmed

value), a delay is initiated before the LDOPGD pin is set.

The delay is programmable by bits 2 and 3 of the LDO Re-

set Control Register. The default delay is 100ms, and this

delay can be programmed to 0, 50, 100, or 150ms.

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