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 2005 Semtech Corp.

www.semtech.com

SC470

POWER MANAGEMENT

Application Information (Cont.)

C10

1uF

R3

20k0

R7

20k0

EN/PSV

1

TON

2

VOUT

3

VCCA

4

FB

5

PGD

6

VSSA

7

PGND

8

DL

9

VDDP

10

ILIM

11

LX

12

DH

13

BST

14

U1

SC470

VOUT

C8

1nF

R1

1M

5VSUS

VBAT

PGOOD

Q1

IRF7811AV

Q2

FDS6676S

C9

1uF

R4 7k87

C1 0.1uF

D1

SOD323

C2

2n2/50V

VBAT

5VSUS

L1

2u2

+

C7

220u/25m

VOUT

R2

10R

0402

0402

0402

0402

C5

56p

0402

R5 49k9

0402

VOUT SWITCH (1)

0402

0603

R6 0R (2)

0402

7343

+

C6

220u/25m

7343

0402

C3

0u1/25V

C4

10u/25V

0603

1210

0603

0402

0603

NOTES

(1) driv en by an open drain with no pullup. LOW = 1.2V out, FLOATIN G = 1V out.

(2) R 6 is not required but aids keeping VSSA s eparate f rom PGN D ex c ept where des ired in lay out.

VBAT = 8V to 20V

VOUT = 1.2V or 1.0V @ 6A

Figure 8: Reference Design For Dynamic Output Switching

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and

maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All

components that are referenced to VSSA should connected to it locally at the chip. VSSA should connect to power

ground at the output capacitor(s) only.

The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate

drives. Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run

them in a “quiet layer” if possible. VSSA may be separated from PGND using a zero Ohm resistor (that will be placed

at the bottom of the output capacitors) to aid in net separation.

Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and

connected directly to them on the same side.

Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling

(including the chip power ground connections). Power components should be placed to minimize loops and reduce

losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use

“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of

the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.

Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling

requirement (and to reduce parasitics) if routed on more than one layer

Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the

current limit resistor located at the device.

We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in

more detail.

Layout Guidelines - TSSOP-14 as an example: