SC470ITSTRT datasheet(10/31 Pages) SEMTECH

10 / 31 page

 2005 Semtech Corp.

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SC470

POWER MANAGEMENT

drop across R

ILIM, a positive over-current exists and the

high side MOSFET will not be allowed to turn on. When

using an external sense resistor R

SENSE is the resistance

of the sense resistor.

The current limit circuitry also protects against negative

over-current (i.e., when the current is flowing from the

load to PGND through the inductor and bottom MOSFET).

In this case, when the bottom MOSFET is turned on, the

phase node, LX, will be higher than PGND initially. The

SC470 monitors the voltage at LX, and if it is greater

than a set threshold voltage of 140mV (nom.) the

bottom MOSFET is turned off. The device then waits for

approximately 2.5µs and then DL goes high for 300ns

(typ.) once more to sense the current. This repeats until

either the over-current condition goes away or the part

latches off due to output over-voltage (see Output

Over-voltage Protection).

Power Good Output

The power good output is an open-drain output and

requires a pull-up resistor. When the output voltage is

20% above or 10% below its set voltage, PGD gets pulled

low. It is held low until the output voltage returns to within

20%/-10% of the output set voltage. PGD is also held

low during start-up and will not be allowed to transition

high until soft-start is over (440 switching cycles) and

the output reaches 90% of its set voltage. There is a 5µs

delay built into the PGD circuitry to prevent false

transitions.

Output Over-Voltage Protection

When the output exceeds 20% of the its set voltage the

low-side MOSFET is latched on. It stays latched on and

the controller is latched off until reset. There is a 5µs

delay built into the OV protection circuit to

prevent false transitions.

Output Under-Voltage Protection

When the output is 30% below its set voltage the output

is latched in a tri-stated condition. It stays latched and

the controller is latched off until reset. There is a 5µs

delay built into the UV protection circuit to

prevent false transitions. Note: to reset from any fault,

VCCA or EN/PSV must be toggled.

Application Information (Cont.)

POR, UVLO and Softstart

An internal power-on reset (POR) occurs when VCCA ex-

ceeds 3V, resetting the fault latch and soft-start counter,

and preparing the PWM for switching. VCCA under-volt-

age lockout (UVLO) circuitry inhibits switching and forces

the DL gate driver high until VCCA rises above 4.2V. At

this time the circuit will come out of UVLO and begin

switching, and with the soft-start circuit enabled, will pro-

gressively limit the output current (by limiting the current

out of the ILIM pin) over a predetermined time period of

440 switching cycles.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time

(for purposes of the on-time one-shot there is an internal

positive offset of 120mV to VOUT during this period to

aid in start-up).

2) 110 cycles at 50% ILIM with normal minimum off-time.

3) 110 cycles at 75% ILIM with normal minimum off-time.

4) 110 cycles at 100% ILIM with normal minimum

off-time.

At this point the output under-voltage and power good

circuitry is enabled. There is 100mV of hysteresis built

into the UVLO circuit and when VCCA falls to 4.1V (nom.)

the output drivers are shut down and tristated.

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving

moderate-sized high-side, and larger low-side power

MOSFETs. An adaptive dead-time circuit monitors the DL

output and prevents the high-side MOSFET from turning

on until DL is fully off (below ~1V). Conversely, it

monitors the phase node, LX, to determine the state of

the high side MOSFET, and prevents the low-side MOSFET

from turning on until DH is fully off (LX below ~1V). Note:

Be sure there is low resistance and low inductance be-

tween the DH and DL outputs to the gate of each

MOSFET.

Dropout Performance

The output voltage adjust range for continuous-

conduction operation is limited by the fixed 550ns

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