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 2005 Semtech Corp.

www.semtech.com

SC1485

POWER MANAGEMENT

Next, looking at the power section, the schematic in Figure 12 below shows the power section and input loop for

OUT2:

C12

2n2/50V

VBAT

L2

VOUT2

+

C17

0402

R12 0R (2)

7343

7343

+

C16

0402

C13

0u1/25V

C14

10u/25V

1210

0603

2u2

220u/25m

220u/25m

S

1

S

2

S

3

G

4

D

5

D

6

D

7

D

8

Q3 IRF7811AV

S

1

S

2

S

3

G

4

D

5

D

6

D

7

D

8

Q4 FDS6676S

Figure 12: Power Section and Input Loop

The schematic has been redrawn to emphasize the input loop. The highest di/dts occur in the input loops and thus

these should be kept as small as possible. The input capacitors should be placed with the highest frequency

capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. Exactly the

same philosophy applies to the OUT1 power section and input loop. Figure 13 below shows an example of the layout

for the power section using these guidelines.

Figure 13: Power Component Placement and Copper Pours