16

 2005 Semtech Corp.

www.semtech.com

SC1485

POWER MANAGEMENT

Layout Guidelines

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and

maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power

ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2

should connect to power ground at their respective output capacitors only.

Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.

Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.

Run them in a “quiet layer” if possible.

Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the

same side.

Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling

(including the chip power ground connections). Power components should be placed to minimize loops and reduce

losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use

“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of

the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.

Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling

requirement (and to reduce parasitics) if routed on more than one layer

Current sense connections must always be made using Kelvin connections to ensure an accurate signal.

We will examine the SC1485 OUT2 reference design used in the Design Procedure section while explaining the

layout guidelines in more detail, using the same generic components for OUT1.

VOUT2

R8

10R

0402

0402

0402

C15

56p

0402

0402

0402

0603

R12 0R (1)

0402

7343

+

C16

220u/25m

7343

C13

0u1/25V

C14

10u/25V

0402

0603

1210

0603

0402

0603

NOTES

(1) R 6 and R 12 aid in keeping VSSA1 and VSSA2 separate f rom PGN D except where desired in lay out.

VOUT2

EN/PSV1

22

TON1

23

VOUT1

24

VCCA1

25

FB1

26

PGD1

27

VSSA1

28

PGND1

1

DL1

2

VDDP1

3

ILIM1

4

LX1

5

DH1

6

BST1

7

EN/PSV2

8

TON2

9

VOUT2

10

VCCA2

11

FB2

12

PGD2

13

VSSA2

14

PGND2

15

DL2

16

VDDP2

17

ILIM2

18

LX2

19

DH2

20

BST2

21

U1

SC1485

C9

1uF

R4

R3

VOUT

C4

1nF

VBAT

R1

5VSUS

PGOOD

Q2

Q1

C10

1uF

R5

C5 0.1uF

D1

SOD323

C6

2n2/50V

5VSUS

VBAT

L1

+

C3

VOUT1

R2

10R

0402

0402

0402

0402

C7

0402

0603

0402

0402

R6 0R (1)

7343

+

C8

7343

0402

C1

0u1/25V

C2

10u/25V

0603

1210

0603

0402

0603

VOUT1

VSSA2

VSSA2

VSSA1

VSSA1

C19

1uF

R9

20k0

R13

20k0

VOUT

C18

1nF

R7

1M

5VSUS

PGOOD

VBAT

Q3

IRF7811AV

Q4

FDS6676S

C20

1uF

R10 7k87

C11 0.1uF

D2

SOD323

C12

2n2/50V

5VSUS

VBAT

L2

2u2

+

C17

220u/25m

Figure 8: Reference Design and Layout Example