address byte indicates if the alert condition is caused by the temperature exceeding THigh_Limit or falling below

the TLow_Limit. The value of the eight bit follows the Polarity bit setting.

Controller drives SDA

Target drives SDA

S

0

0

0

1

1

0

0

1

A

A6

A5

A4

A3

A2

A1

A0

S

NA

P

START

ACK from Target

NACK from Controller

STOP

SMBus Alert Func on

Target Address from Device

Alert Status

ALERT

Figure 7-10. SMBus Alert Response

If multiple devices on the bus respond to the SMBus alert command, arbitration during the device address

portion of the SMBus alert command determines which devices the ALERT pin is activated. The device with the

lowest address wins the arbitration. On winning the arbitration, the TMP113 inactivates the ALERT pin and/or

clears the status bit. To prevent the device with lowest I2C address in continuous conversion mode sees the alert

line and halt others with higher I2C address to report the alert, the controller has to temporarily disable the Alert

mode in device with smallest I2C address until all alerts in the system are cleared.

7.5.4.5 Time-Out Function

The TMP113 resets the serial interface if the SCL line is held low by the controller or the SDA line is held low

by the TMP113 for 30ms (typical) between a START and STOP condition. The TMP113 releases the SDA line

if the SCL pin is pulled low and waits for a START condition from the controller. To avoid activating the timeout

function, maintain a communication speed of at least 1kHz for the SCL operating frequency. If another device on

the bus is holding the SDA pin low, the TMP113 does not reset.

7.5.4.6 Coexist on I3C Mixed Bus

A bus with both I3C and I2C interfaces is referred to as a mixed bus with clock speeds up to 12.5MHz. The

TMP113 is an I2C device that can be on the same bus that has an I3C device attached, as the TMP113

incorporates a spike suppression filter of 50ns on the SDA and SCL pins to avoid any interference to the bus

when communicating with I3C devices.

TMP113

SBOSAJ5 – DECEMBER 2024

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