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POWER MANAGEMENT

SC2441

Applications Information (Cont.)

4) Shorten the gate driver path. Integrity of the gate drive

(voltage level, leading and falling edges) is important for

circuit operation and efficiency. Short and wide gate drive

traces reduce trace inductances. Bond wire inductance is

about 2~3nH. If the length of the PCB trace from the gate

driver to the MOSFET gate is 1 inch, the trace inductance

will be about 25nH. If the gate drive current is 2A with

10ns rise and falling times, the voltage drops across the

bond wire and the PCB trace will be 0.6V and 5V

respectively. This may slow down the switching transient of

the MOSFET’s. These inductances may also ring with the

gate capacitance.

5) Put the decoupling capacitor for the gate drive power

supplies (BST and VCC) close to the IC and power ground.

Control Section

6) The frequency-setting resistor Rosc should be placed

close to Pin 10. Trace length from this resistor to the analog

ground should be minimized.

7) Solder the VCC decoupling capacitor next to the VCC

and power ground PGND pins.

8) Place the combi-sense components away from the power

circuit and close to the corresponding CS+ and CS- pins.

Use X7R type ceramic capacitors for combi-sensing due

to their thermal stability.

9) Use an isolated local ground plane for the controller

and tie it to the negative side of output capacitor bank.

PC Board Layout Issues

Circuit board layout is very important for the proper

operation of high frequency switching power converters. A

power ground plane is required to reduce ground bounces.

The followings are suggested for proper layout.

Power Stage

1) Separate the power ground from the signal ground. In

SC2441 the power ground PGND should be tied to the

source terminal of lower MOSFETs. The signal ground AGND

should be tied to the negative terminal of the output

capacitor (ouput return terminal).

2) Minimize the size of pulse current loop. Place the top

MOSFET, the bottom MOSFET and the input capacitors

close to each other with short and wide traces. In addition

to the aluminum energy storage capacitors, add multi-layer

ceramic (MLC) capacitors from the input to the power

ground to improve high frequency bypass.

3) Reduce high frequency voltage ringing. Widen and

shorten the drain and source traces of the MOSFET’s to

reduce stray inductances. Add a small RC snubber if

necessary to reduce the high frequency ringing at the phase

node. Sometimes slowing down the gate drive signal also

helps in reducing the high frequency ringing at the phase

node.

A note for Vin = 12V application

Figure 21 shows an application where the input voltage is 12V. A LDO is used to provide 5V bias for SC2441. The

voltages at BST1 (Pin 25) and BST2 (Pin 18) should not exceed their maximum voltage rating (20V).