SC1404 datasheet(12/25 Pages) SEMTECH

12 / 25 page

 2004 Semtech Corp.

www.semtech.com

SC1404

PRELIMINARY

POWER MANAGEMENT

shown below. The mosfet current is a trapezoid waveform with

values equal to:

∆I

LOAD

MIN

−

∆I

LOAD

MAX

∆IL

⋅

−

⋅

Vin

()

MAX

MIN

RMS

⋅

As input voltage decreases, the duty cycle increases and the ripple

current decrease, and overall the RMS mosfet current will increase.

The conduction losses are then given by the formula below, where

Rds(on) is 18m-ohm for the IRF7413 at room temperature. Note

that Rds(on) increases with temperature.

RMS

ds(on)

CONDUCTION

⋅

The mosfet switching loss is estimated according to:

OUT

RSS

SWITCHING

⋅

Crss is the mosfet’s reverse transfer capacitance, 240pF for

IRF7413. Ig is the gate driver current, which is 1A for SC1403.

The mosfet gate drive loss is estimated from:

GATE

Vgfs

⋅

Cg is the effective gate capacitance, equal to the Total Gate Charge

divided by VGS, from the vendor datasheet, and is 7.9nF for the

IRF7413. Vgfs is the final gate-source voltage, 5V in this case.

The total mosfet loss is the sum of the three loss components.

GATE

SWITCHING

CONDUCTION

TOTAL_DISS

The mosfet dissipation under conditions of 15V input, 6A load,

and ambient temperature of 25C, can be determined as:

DNOM = 0.22

∆IL = 1.26A

IMIN = 5.37A

IMAX = 6.63A

IRMS = 4.88A

Rds(on) (100C) = 18 mohm

PCONDUCTION = 429mW

PSWITCHING = 97mW

PGATE = 30mW

PTOTAL_DISS = 429 + 97 + 30 = 556 mW

The junction temperature rise resulting from the power dissipa-

tion is calculated as:

∆T

⋅

T is the total device dissipation, and θJA is the package thermal

resistance, which is 50°C/W for the IRf7413. The junction tem-

perature rise is then:

∆T

J = 0.556W

50°C/W = 27.8°

This is an acceptable temperature rise, so no special heat sinking

is required.

Designing the Loop

A good loop design is a combination of the power train and com-

pensation design. In the SC1404, the control-to-output/power train

response is dominated by the load impedance, the inductor, out-

put capacitance, and the ESR of the output caps. The low fre-

quency gain is dominated by the output load impedance and the

effective current sense resistor. Inherent to Virtual Current SenseTM,

there is one additional low frequency pole sitting between 100Hz

and 1kHz and a zero between 15kHz and 25kHz. he output of

error amplifier COMP pin is available for external compensation. A

traditional pole-zero-pole compensation is not necessary in the

design using SC1404, a simple high frequency pole is usually

sufficient.

Single-Pole Compensation Method

Given parameters:

Vin = 19V, Vout = 3.3V @ 2.2A,

Output impedance, Ro = 3.3V/2.2A = 1.5 Ω ,

Panasonic SP cap, Co = 180uF, Resr = 15 Ω

m ,

Output inductor, Lo = 4.7uH

Switching frequency, Fs = 300kHz

Simulated Control-to-Output gain & phase response (up to

100kHz) is plotted below.

-50

-40

-30

-20

-10

1.00E+02

1.00E+03

1.00E+04

1.00E+05

f (Hz)

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