HT46R01 datasheet(20/60 Pages) HOLTEK

20 / 60 page

HT46R01/HT46R02/HT46R03

Rev. 1.00

September 21, 2007

Timer/Event Counters. Before the timers can be used, it

is essential that the appropriate Timer Control Register

is fully programmed with the right data to ensure its cor-

rect operation, a process that is normally carried out

during program initialisation.

To choose which of the three modes the timer is to oper-

ate in, either in the timer mode, the event counting mode

or the pulse width measurement mode, bits 7 and 6 of

the Timer Control Register, which are known as the bit

pair T0M1/T0M0 or T1M1/T1M0 respectively, depend-

ing upon which timer is used, must be set to the required

logic levels. The timer-on bit, which is bit 4 of the Timer

Control Register and known as T0ON or T1ON, depend-

ing upon which timer is used, provides the basic on/off

control of the respective timer. Setting the bit high allows

the counter to run, clearing the bit stops the counter. For

timers that have prescalers, bits 0~2 of the Timer Con-

trol Register determine the division ratio of the input

clock prescaler. The prescaler bit settings have no effect

if an external clock source is used. If the timer is in the

event count or pulse width measurement mode, the ac-

tive transition edge level type is selected by the logic

level of bit 3 of the Timer Control Register which is

known as T0E or T1E, depending upon which timer is

used.

Configuring the Timer Mode

In this mode, the timer can be utilized to measure fixed

time intervals, providing an internal interrupt signal each

time the counter overflows. To operate in this mode, the

bit pair, T0M1/T0M0 or T1M1/T1M0 depending upon

which timer is used, must be set to 1 and 0 respectively.

In this mode the internal clock is used as the timer clock.

Note that for Timer/Event Counter 0, the timer input

clock source is either fSYS or the RTC oscillator. How-

ever, this timer clock source is further divided by a

prescaler, the value of which is determined by the bits

T0PSC2~T0PSC0 in the Timer Control Register. For

Timer/Event Counter 1, the timer input clock source

fSYS/4 or the RTC oscillator. There is no prescaler func-

tion for Timer/Event Counter 1. The timer-on bit, T0ON

or T1ON, depending upon which timer is used, must be

set high to enable the timer to run. Each time an internal

clock high to low transition occurs, the timer increments

by one; when the timer is full and overflows, an interrupt

signal is generated and the timer will preload the value

already loaded into the preload register and continue

counting. A timer overflow condition and corresponding

internal interrupt is one of the wake-up sources, how-

ever, the internal interrupts can be disabled by ensuring

that the ET0I or ET1I bits of the INTC0 register are reset

to zero.

b 7

T 1 E

T 1 O N

T 1 M 0

T 1 M 1

b 0

T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r

T M R 1 C

H T 4 6 R 0 2 / H T 4 6 R 0 3

N o t i m p l e m e n t e d , r e a d a s " 0 "

E v e n t C o u n t e r a c t i v e e d g e s e l e c t

1 : c o u n t o n f a l l i n g e d g e

0 : c o u n t o n r i s i n g e d g e

P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t

1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e

0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e

1 : e n a b l e

0 : d i s a b l e

T 0 M 1

T 0 M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

O p e r a t i n g m o d e s e l e c t

T i m e r c l o c k s o u r c e

1 : R T C

0 : f S Y S / 4

T 1 S

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

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