HT45R38 datasheet(21/49 Pages) HOLTEK

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HT45R38

Rev. 1.00

December 13, 2006

Input/Output Ports

There are 29 bidirectional input/output lines in the

microcontroller, labeled as PA, PB, PC and PE, which

are mapped to the data memory at [12H], [14H], [16H]

and [18H] respectively. All of these I/O ports can be

used for input and output operations. For input opera-

tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

² (m=12H, 14H, 16H or 18H). For output operation,

all the data is latched and remains unchanged until the

output latch is rewritten.

Each I/O line has its own control register, known as

PAC, PBC, PCC and PEC, to control the input/output

configuration. With this control register, a CMOS output

or schmitt trigger input with or without pull-high resistor

structures can be reconfigured dynamically, i.e.

on-the-fly, under software control. To function as an in-

put, the corresponding latch of the control register must

written with a

²1². The input source also depends on the

control register. If the control register bit is

²1², the input

will read the pad state. If the control register bit is

²0²,

the contents of the latches will move to the internal bus.

The latter is possible in the

²read-modify-write² instruc-

tion.

For an output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, 17H and 19H. After a chip reset, the port control

registers will default to a high state, which is an input

condition. They may be floating or be pulled high if

pull-high resistors are connected. Each bit of these in-

put/output latches can be set or cleared by

²SET [m].i²

and

²CLR [m].i² (m=12H, 14H, 16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The highest bits, 5,6 and 7, of port E are not

physically implemented; on reading them a

²0² is re-

turned whereas writing to them results in no operation.

Each I/O line has a pull-high configuration option. It

should be noted that an input line without a connected

pull-high resistor will be in a floating state.

PA0, PA1, PA3, PA4, PA5 and PA6 are pin-shared with

PWM0, PWM1, INT0, INT1, TMR0 and TMR1 pins, re-

spectively.

The PE port can also be used as A/D converter inputs.

The A/D function will be described later.

The PWM outputs are shared with pins PA0/PA1. If the

PWM function is enabled, the PWM0/PWM1 signals will

appear on PA0/PA1. Note that PA0/PA1 must be setup

as outputs for the PWM output to function. The I/O func-

tions of PA0/PA1 are as shown.

I/O Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PWM)

O/P

(PWM)

PA0

PA1

Logical

Input

Logical

Output

Logical

Input

PWM0

PWM1

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

V D D

O P 0 ~ O P 7

I N T 0 f o r P A 3 O n l y

I N T 0 f o r P A 4 O n l y

T M R 0 f o r P A 5 O n l y

T M R 1 f o r P A 6 O n l y

S y s t e m W a k e - u p ( P A o n l y )

R e a d D a t a R e g i s t e r

C o n t r o l B i t P u l l - h i g h

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 / P W M 0

P A 1 / P W M 1

P A 2

P A 3 / I N T 0

P A 4 / I N T 1

P A 5 / T M R 0

P A 6 / T M R 1

P A 7

P B 0 ~ P B 7

P C 0 ~ P C 7

P E 0 / A N 0 ~ P E 4 / A N 4

C K

E N ( P W M x )

P A 0 / P A 1

P W M 0 / P W M 1

Input/Output Ports

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