HT45R38 datasheet(13/49 Pages) HOLTEK

13 / 49 page

HT45R38

Rev. 1.00

December 13, 2006

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator. No other external compo-

nents are required. Instead of a crystal, a resonator can

also be connected between OSC1 and OSC2 to get a

frequency reference, but two external capacitors con-

nected between OSC1, OSC2 and ground are required,

if the oscillator frequency is less than 1MHz.

The WDT oscillator is a free running on-chip RC oscilla-

tor which requires no external components. Even if the

system enters the Power Down Mode, where the sys-

tem clock is stopped, the WDT oscillator will continue to

operate with a period of approximately 65

msat5V.The

WDT oscillator can be disabled by a configuration option

to conserve power.

Watchdog Timer

- WDT

The WDT clock can be sourced from its own dedicated

internal oscillator (WDT oscillator), or from the or in-

struction clock, which is the system clock divided by 4.

The choice is determined via a configuration option. The

WDT timer is designed to prevent a software malfunc-

tion or sequence from jumping to an unknown location

with unpredictable results. The Watchdog Timer can be

disabled by a configuration option. If the Watchdog

Timer is disabled, any executions related to the WDT re-

sult in no operation.

The WDT clock source is first divided by 256. If the inter-

nal WDT oscillator is used ,this gives a nominal time-out

period of approximately 17ms at 5V. This time-out pe-

riod may vary with temperatures, VDD and process vari-

ations. By using the WDT prescaler, longer time-out

periods can be realised. Writing data to the WS2, WS1,

WS0 bits in the WDTS register, can give different

time-out periods. If WS2, WS1, and WS0 are all equal to

1, the division ratio will be 1:128, and the maximum

time-out period will be 2.1s at 5V. If the internal WDT os-

cillator is disabled, the WDT clock may still come from

the instruction clock and operate in the same manner

except that in the Power Down state the WDT will stop

counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. The

high nibble and bit 3 of the WDTS can be used for user

defined flags.

If the device operates in a noisy environment, using the

internal WDT oscillator is the recommended choice,

since the HALT instruction will stop the system clock.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

WDTS (09H) Register

The WDT overflow under normal operation will generate

²chip reset² and set the status bit ²TO². But in the

Power Down mode, the overflow will generate a

²warm

reset

², where only the Program Counter and SP are re-

set to zero. To clear the contents of the WDT, including

the WDT prescaler, three methods can be used; an ex-

ternal reset (a low level to RES), a software instruction

and a

²HALT² instruction. The software instruction in-

cludes

²CLR WDT² instruction and the instruction pair -

²CLR WDT1² and ²CLR WDT2². Of these two types of

instruction, only one can be active depending on the

configuration option

-²CLR WDT times selection op -

tion

².Ifthe ²CLR WDT² is selected, i.e. CLRWDT times

equal one, any execution of the

²CLR WDT² instruction

will clear the WDT. In the case that

²CLR WDT1² and

²CLR WDT2² are chosen, i.e. CLRWDT times equal

two, these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip as a

result of a time-out.

Power Down Operation

- HALT

The Power Down mode is initialized by the

²HALT² in-

struction and results in the following...

· The system oscillator will be turned off but the WDT

oscillator keeps running, if the internal WDT oscillator

has been selected as the WDT source clock.

· The contents of the on chip RAM and registers remain

unchanged.

· The WDT and WDT prescaler will be cleared and will

resume counting, if the internal WDT oscillator has

been selected as the WDT source clock

· All of the I/O ports will maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the Power Down Mode by means

of an external reset, an interrupt, an external falling

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

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