HT36M4

Rev. 1.10

8

March 14, 2007

The wavetable function registers are defined between

20H~2AH. The unused space before 40H is reserved

for future expanded usage and reading these locations

will return the result 00H. The general purpose data

memory, addressed from 40H to FFH, is used for data

and control information under instruction command.

All data memory areas can handle arithmetic, logic, in-

crement, decrement and rotate operations directly. Ex-

cept for some dedicated bits, each bit in the data

memory can be set and reset by the

²SET [m].i² and

²CLR [m].i² instructions, respectively. They are also indi-

rectly accessible through Memory pointer registers

(MP0;01H, MP1;03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] access data memory pointed

to by MP0 (01H) and MP1 (03H) respectively. Reading

location 00H or 02H directly will return the result 00H.

And writing directly results in no operation.

The function of data movement between two indirect ad-

dressing registers, is not supported. The memory

pointer registers, MP0 and MP1, are 8-bit register which

can be used to access the data memory by combining

corresponding indirect addressing registers.

Accumulator

The accumulator closely relates to ALU operations. It is

mapped to location 05H of the data memory and it can

operate with immediate data. The data movement be-

tween two data memory locations must pass through

the accumulator.

Arithmetic and Logic Unit

- ALU

This circuit performs 8-bit arithmetic and logic operation.

The ALU provides the following functions:

The ALU not only saves the results of a data operation but

can also change the status register.

Status Register

- STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF) and Watchdog time-out flag

(TO). It also records the status information and controls the

operation sequence.

With the exception of the TO and PDF flags, bits in the

status register can be altered by instructions like any

other register. Any data written into the status register

will not change the TO or PDF flags. In addition, it

should be noted that operations related to the status

register may give different results from those intended.

The TO and PDF flags can only be changed by system

power up, Watchdog Timer overflow, executing the

²HALT² instruction and clearing the Watchdog Timer.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting a subroutine call, the status register will not be

automatically pushed onto the stack. If the contents of

status are important and the subroutine can corrupt the

status register, the programmer must take precautions

to save it properly.

Bit No.

Label

Function

0C

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate

through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

2

Z

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

3OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

4

PDF

PDF is cleared by either a system power-up or executing the

²CLR WDT² instruction. PDF is

set by executing the

²HALT² instruction.

5TO

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

6~7

¾

Unused bit, read as

²0²

STATUS (0AH) Register